mirror of git://gcc.gnu.org/git/gcc.git
This is almost exclusively Jivan's work. His original post:
> https://www.mail-archive.com/gcc-patches@gcc.gnu.org/msg336483.html This patch is primarily meant to improve the code we generate for FP rounding such as ceil/floor. It also addresses some unnecessary sign extensions in the same areas. RISC-V's FP conversions have a bit of undesirable behavior that make them non-suitable as-is for ceil/floor and other related functions. These deficiencies are addressed in the Zfa extension, but there's no reason not to pick up a nice improvement when we can. Basically we can still use the basic FP conversions for floor/ceil and friends when we don't care about inexact exceptions by checking for the special cases first, then emitting the conversion when the special cases don't apply. That's still much faster than calling into glibc. The redundant sign extensions are eliminated using the same trick Jivan added last year, just in a few more places ;-) This eliminates roughly 10% of the dynamic instruction count for imagick. But more importantly it's about a 17% performance improvement for that workload within spec. This has been bootstrapped as well as regression tested in a cross environment. It's also successfully built & run specint/specfp correctly. Pushing to the trunk and the coordination branch momentarily. gcc/ * config/riscv/iterators.md (fix_ops, fix_uns): New iterators. (RINT, rint_pattern, rint_rm): Remove unused iterators. * config/riscv/riscv-protos.h (get_fp_rounding_coefficient): Prototype. * config/riscv/riscv-v.cc (get_fp_rounding_coefficient): Externalize. external linkage. * config/riscv/riscv.md (UNSPEC_LROUND): Remove. (fix_trunc<ANYF:mode><GPR:mode>2): Replace with ... (<fix_uns>_trunc<ANYF:mode>si2): New expander & associated insn. (<fix_uns>_trunc<ANYF:mode>si2_ext): New insn. (<fix_uns>_trunc<ANYF:mode>di2): Likewise. (l<rint_pattern><ANYF:mode><GPR:mode>2): Replace with ... (lrint<ANYF:mode>si2): New expander and associated insn. (lrint<ANYF:mode>si2_ext, lrint<ANYF:mode>di2): New insns. (<round_pattern><ANYF:mode>2): Replace with.... (l<round_pattern><ANYF:mode>si2): New expander and associated insn. (l<round_pattern><ANYF:mode>si2_sext): New insn. (l<round_pattern><ANYF:mode>di2): Likewise. (<round_pattern><ANYF:mode>2): New expander. gcc/testsuite/ * gcc.target/riscv/fix.c: New test. * gcc.target/riscv/round.c: New test. * gcc.target/riscv/round_32.c: New test. * gcc.target/riscv/round_64.c: New test.
This commit is contained in:
Jivan Hakobyan
Jeff Law
parent
0b2735e079
commit
f652a35877
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@ -196,6 +196,13 @@
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(define_code_iterator bitmanip_rotate [rotate rotatert])
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;; These code iterators allow the signed and unsigned fix operations to use
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;; the same template.
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(define_code_iterator fix_ops [fix unsigned_fix])
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(define_code_attr fix_uns [(fix "fix") (unsigned_fix "fixuns")])
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;; -------------------------------------------------------------------
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;; Code Attributes
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;; -------------------------------------------------------------------
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@ -312,11 +319,6 @@
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;; Int Iterators.
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;; -------------------------------------------------------------------
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;; Iterator and attributes for floating-point rounding instructions.
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(define_int_iterator RINT [UNSPEC_LRINT UNSPEC_LROUND])
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(define_int_attr rint_pattern [(UNSPEC_LRINT "rint") (UNSPEC_LROUND "round")])
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(define_int_attr rint_rm [(UNSPEC_LRINT "dyn") (UNSPEC_LROUND "rmm")])
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;; Iterator and attributes for quiet comparisons.
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(define_int_iterator QUIET_COMPARISON [UNSPEC_FLT_QUIET UNSPEC_FLE_QUIET])
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(define_int_attr quiet_pattern [(UNSPEC_FLT_QUIET "lt") (UNSPEC_FLE_QUIET "le")])
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@ -711,6 +711,7 @@ bool gather_scatter_valid_offset_p (machine_mode);
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HOST_WIDE_INT estimated_poly_value (poly_int64, unsigned int);
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bool whole_reg_to_reg_move_p (rtx *, machine_mode, int);
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bool splat_to_scalar_move_p (rtx *);
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rtx get_fp_rounding_coefficient (machine_mode);
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}
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/* We classify builtin types into two classes:
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@ -4494,7 +4494,7 @@ vls_mode_valid_p (machine_mode vls_mode)
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All double floating point will be unchanged for ceil if it is
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greater than and equal to 4503599627370496.
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*/
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static rtx
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rtx
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get_fp_rounding_coefficient (machine_mode inner_mode)
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{
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REAL_VALUE_TYPE real;
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@ -64,7 +64,6 @@
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UNSPEC_ROUNDEVEN
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UNSPEC_NEARBYINT
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UNSPEC_LRINT
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UNSPEC_LROUND
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UNSPEC_FMIN
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UNSPEC_FMAX
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UNSPEC_FMINM
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@ -1919,21 +1918,48 @@
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;;
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;; ....................
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(define_insn "fix_trunc<ANYF:mode><GPR:mode>2"
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[(set (match_operand:GPR 0 "register_operand" "=r")
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(fix:GPR
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(define_expand "<fix_uns>_trunc<ANYF:mode>si2"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(fix_ops:SI
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(match_operand:ANYF 1 "register_operand" " f")))]
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"TARGET_HARD_FLOAT || TARGET_ZFINX"
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"fcvt.<GPR:ifmt>.<ANYF:fmt> %0,%1,rtz"
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{
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if (TARGET_64BIT)
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{
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rtx t = gen_reg_rtx (DImode);
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emit_insn (gen_<fix_uns>_trunc<ANYF:mode>si2_sext (t, operands[1]));
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t = gen_lowpart (SImode, t);
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SUBREG_PROMOTED_VAR_P (t) = 1;
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SUBREG_PROMOTED_SET (t, SRP_SIGNED);
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emit_move_insn (operands[0], t);
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DONE;
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}
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})
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(define_insn "*<fix_uns>_trunc<ANYF:mode>si2"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(fix_ops:SI
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(match_operand:ANYF 1 "register_operand" " f")))]
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"TARGET_HARD_FLOAT || TARGET_ZFINX"
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"fcvt.w<u>.<ANYF:fmt> %0,%1,rtz"
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[(set_attr "type" "fcvt_f2i")
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(set_attr "mode" "<ANYF:MODE>")])
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(define_insn "fixuns_trunc<ANYF:mode><GPR:mode>2"
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[(set (match_operand:GPR 0 "register_operand" "=r")
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(unsigned_fix:GPR
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(define_insn "<fix_uns>_trunc<ANYF:mode>si2_sext"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(sign_extend:DI (fix_ops:SI
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(match_operand:ANYF 1 "register_operand" " f"))))]
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"TARGET_64BIT && (TARGET_HARD_FLOAT || TARGET_ZFINX)"
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"fcvt.w<u>.<ANYF:fmt> %0,%1,rtz"
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[(set_attr "type" "fcvt_f2i")
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(set_attr "mode" "<ANYF:MODE>")])
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(define_insn "<fix_uns>_trunc<ANYF:mode>di2"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(fix_ops:DI
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(match_operand:ANYF 1 "register_operand" " f")))]
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"TARGET_HARD_FLOAT || TARGET_ZFINX"
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"fcvt.<GPR:ifmt>u.<ANYF:fmt> %0,%1,rtz"
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"TARGET_64BIT && (TARGET_HARD_FLOAT || TARGET_ZFINX)"
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"fcvt.l<u>.<ANYF:fmt> %0,%1,rtz"
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[(set_attr "type" "fcvt_f2i")
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(set_attr "mode" "<ANYF:MODE>")])
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@ -1955,17 +1981,170 @@
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[(set_attr "type" "fcvt_i2f")
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(set_attr "mode" "<ANYF:MODE>")])
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(define_insn "l<rint_pattern><ANYF:mode><GPR:mode>2"
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[(set (match_operand:GPR 0 "register_operand" "=r")
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(unspec:GPR
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(define_expand "lrint<ANYF:mode>si2"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(unspec:SI
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[(match_operand:ANYF 1 "register_operand" " f")]
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RINT))]
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UNSPEC_LRINT))]
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"TARGET_HARD_FLOAT || TARGET_ZFINX"
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"fcvt.<GPR:ifmt>.<ANYF:fmt> %0,%1,<rint_rm>"
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{
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if (TARGET_64BIT)
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{
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rtx t = gen_reg_rtx (DImode);
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emit_insn (gen_lrint<ANYF:mode>si2_sext (t, operands[1]));
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t = gen_lowpart (SImode, t);
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SUBREG_PROMOTED_VAR_P (t) = 1;
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SUBREG_PROMOTED_SET (t, SRP_SIGNED);
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emit_move_insn (operands[0], t);
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DONE;
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}
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})
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(define_insn "*lrint<ANYF:mode>si2"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(unspec:SI
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[(match_operand:ANYF 1 "register_operand" " f")]
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UNSPEC_LRINT))]
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"TARGET_HARD_FLOAT || TARGET_ZFINX"
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"fcvt.w.<ANYF:fmt> %0,%1,dyn"
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[(set_attr "type" "fcvt_f2i")
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(set_attr "mode" "<ANYF:MODE>")])
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(define_insn "<round_pattern><ANYF:mode>2"
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(define_insn "lrint<ANYF:mode>si2_sext"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(sign_extend:DI (unspec:SI
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[(match_operand:ANYF 1 "register_operand" " f")]
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UNSPEC_LRINT)))]
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"TARGET_64BIT && (TARGET_HARD_FLOAT || TARGET_ZFINX)"
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"fcvt.w.<ANYF:fmt> %0,%1,dyn"
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[(set_attr "type" "fcvt_f2i")
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(set_attr "mode" "<ANYF:MODE>")])
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(define_insn "lrint<ANYF:mode>di2"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(unspec:DI
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[(match_operand:ANYF 1 "register_operand" " f")]
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UNSPEC_LRINT))]
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"TARGET_64BIT && (TARGET_HARD_FLOAT || TARGET_ZFINX)"
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"fcvt.l.<ANYF:fmt> %0,%1,dyn"
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[(set_attr "type" "fcvt_f2i")
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(set_attr "mode" "<ANYF:MODE>")])
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(define_expand "l<round_pattern><ANYF:mode>si2"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(unspec:SI
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[(match_operand:ANYF 1 "register_operand" " f")]
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ROUND))]
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"TARGET_HARD_FLOAT || TARGET_ZFINX"
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{
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if (TARGET_64BIT)
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{
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rtx t = gen_reg_rtx (DImode);
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emit_insn (gen_l<round_pattern><ANYF:mode>si2_sext (t, operands[1]));
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t = gen_lowpart (SImode, t);
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SUBREG_PROMOTED_VAR_P (t) = 1;
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SUBREG_PROMOTED_SET (t, SRP_SIGNED);
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emit_move_insn (operands[0], t);
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DONE;
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}
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})
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(define_insn "*l<round_pattern><ANYF:mode>si2"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(unspec:SI
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[(match_operand:ANYF 1 "register_operand" " f")]
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ROUND))]
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"TARGET_HARD_FLOAT || TARGET_ZFINX"
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"fcvt.w.<ANYF:fmt> %0,%1,<round_rm>"
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[(set_attr "type" "fcvt_f2i")
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(set_attr "mode" "<ANYF:MODE>")])
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(define_insn "l<round_pattern><ANYF:mode>si2_sext"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(sign_extend:DI (unspec:SI
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[(match_operand:ANYF 1 "register_operand" " f")]
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ROUND)))]
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"TARGET_64BIT && (TARGET_HARD_FLOAT || TARGET_ZFINX)"
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"fcvt.w.<ANYF:fmt> %0,%1,<round_rm>"
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[(set_attr "type" "fcvt_f2i")
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(set_attr "mode" "<ANYF:MODE>")])
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(define_insn "l<round_pattern><ANYF:mode>di2"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(unspec:DI
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[(match_operand:ANYF 1 "register_operand" " f")]
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ROUND))]
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"TARGET_64BIT && (TARGET_HARD_FLOAT || TARGET_ZFINX)"
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"fcvt.l.<ANYF:fmt> %0,%1,<round_rm>"
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[(set_attr "type" "fcvt_f2i")
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(set_attr "mode" "<ANYF:MODE>")])
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(define_expand "<round_pattern><ANYF:mode>2"
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[(set (match_operand:ANYF 0 "register_operand" "=f")
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(unspec:ANYF
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[(match_operand:ANYF 1 "register_operand" " f")]
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ROUND))]
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"TARGET_HARD_FLOAT && (TARGET_ZFA
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|| flag_fp_int_builtin_inexact || !flag_trapping_math)"
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{
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if (TARGET_ZFA)
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emit_insn (gen_<round_pattern><ANYF:mode>_zfa2 (operands[0],
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operands[1]));
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else
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{
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rtx reg;
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rtx label = gen_label_rtx ();
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rtx end_label = gen_label_rtx ();
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rtx abs_reg = gen_reg_rtx (<ANYF:MODE>mode);
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rtx coeff_reg = gen_reg_rtx (<ANYF:MODE>mode);
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rtx tmp_reg = gen_reg_rtx (<ANYF:MODE>mode);
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riscv_emit_move (tmp_reg, operands[1]);
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riscv_emit_move (coeff_reg,
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riscv_vector::get_fp_rounding_coefficient (<ANYF:MODE>mode));
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emit_insn (gen_abs<ANYF:mode>2 (abs_reg, operands[1]));
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riscv_expand_conditional_branch (label, LT, abs_reg, coeff_reg);
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emit_jump_insn (gen_jump (end_label));
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emit_barrier ();
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emit_label (label);
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switch (<ANYF:MODE>mode)
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{
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case SFmode:
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reg = gen_reg_rtx (SImode);
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emit_insn (gen_l<round_pattern>sfsi2 (reg, operands[1]));
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emit_insn (gen_floatsisf2 (abs_reg, reg));
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break;
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case DFmode:
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if (TARGET_64BIT)
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{
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reg = gen_reg_rtx (DImode);
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emit_insn (gen_l<round_pattern>dfdi2 (reg, operands[1]));
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emit_insn (gen_floatdidf2 (abs_reg, reg));
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}
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else
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{
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reg = gen_reg_rtx (SImode);
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emit_insn (gen_l<round_pattern>dfsi2 (reg, operands[1]));
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emit_insn (gen_floatsidf2 (abs_reg, reg));
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}
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break;
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default:
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gcc_unreachable ();
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}
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emit_insn (gen_copysign<ANYF:mode>3 (tmp_reg, abs_reg, operands[1]));
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emit_label (end_label);
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riscv_emit_move (operands[0], tmp_reg);
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}
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DONE;
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})
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(define_insn "<round_pattern><ANYF:mode>_zfa2"
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[(set (match_operand:ANYF 0 "register_operand" "=f")
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(unspec:ANYF
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[(match_operand:ANYF 1 "register_operand" " f")]
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|
|
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|
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@ -0,0 +1,34 @@
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/* { dg-do compile } */
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/* { dg-options "-march=rv64gc -mabi=lp64d" } */
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/* { dg-skip-if "" { *-*-* } { "-O0" } } */
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int
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foo (double n)
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{
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return n;
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}
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int
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foo_1 (float n)
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{
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return n;
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}
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unsigned int
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foo_2 (double n)
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{
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return n;
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}
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|
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unsigned int
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foo_3 (float n)
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{
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return n;
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}
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|
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/* { dg-final { scan-assembler-times {\mfcvt.w.d} 1 } } */
|
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/* { dg-final { scan-assembler-times {\mfcvt.w.s} 1 } } */
|
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/* { dg-final { scan-assembler-times {\mfcvt.wu.d} 1 } } */
|
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/* { dg-final { scan-assembler-times {\mfcvt.wu.s} 1 } } */
|
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/* { dg-final { scan-assembler-not "\\ssext.w\\s" } } */
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|
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@ -0,0 +1,144 @@
|
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#include <math.h>
|
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|
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extern void abort (void);
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extern void exit (int);
|
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|
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#define NEQ(a, b) (fabs((a) - (b)) > 0.000001)
|
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|
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#define DECL_FUNC(TYPE1, TYPE2, ROUND) \
|
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__attribute__ ((noinline, noclone)) TYPE2 \
|
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convert_##TYPE1##_to_##TYPE2##_##ROUND (TYPE1 N) \
|
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{ \
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return ROUND (N); \
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}
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|
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#define DECL_ALL_ROUNDS_FOR(ROUND_FUNC) \
|
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DECL_FUNC(float, float, ROUND_FUNC) \
|
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DECL_FUNC(double, double, ROUND_FUNC) \
|
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DECL_FUNC(double, int, ROUND_FUNC) \
|
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DECL_FUNC(double, long, ROUND_FUNC) \
|
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DECL_FUNC(float, int, ROUND_FUNC) \
|
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DECL_FUNC(float, long, ROUND_FUNC)
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|
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|
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DECL_ALL_ROUNDS_FOR(round)
|
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DECL_ALL_ROUNDS_FOR(ceil)
|
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DECL_ALL_ROUNDS_FOR(floor)
|
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DECL_ALL_ROUNDS_FOR(trunc)
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DECL_ALL_ROUNDS_FOR(nearbyint)
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|
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#define TEST_ROUND(TYPE1, TYPE2, N, N_R, ROUND) \
|
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if (NEQ (convert_##TYPE1##_to_##TYPE2##_##ROUND (N), N_R)) \
|
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abort ();
|
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|
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|
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int main () {
|
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|
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/* Round */
|
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TEST_ROUND(double, double, -4.8, -5.0, round);
|
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TEST_ROUND(double, double, -4.2, -4.0, round);
|
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TEST_ROUND(double, double, 4.8, 5.0, round);
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TEST_ROUND(double, double, 4.2, 4.0, round);
|
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|
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TEST_ROUND(double, int, -4.8, -5, round);
|
||||
TEST_ROUND(double, int, -4.2, -4, round);
|
||||
TEST_ROUND(double, int, 4.8, 5, round);
|
||||
TEST_ROUND(double, int, 4.2, 4, round);
|
||||
|
||||
TEST_ROUND(double, long, -4.8, -5, round);
|
||||
TEST_ROUND(double, long, -4.2, -4, round);
|
||||
TEST_ROUND(double, long, 4.8, 5, round);
|
||||
TEST_ROUND(double, long, 4.2, 4, round);
|
||||
|
||||
TEST_ROUND(float, long, -4.8, -5, round);
|
||||
TEST_ROUND(float, long, -4.2, -4, round);
|
||||
TEST_ROUND(float, long, 4.8, 5, round);
|
||||
TEST_ROUND(float, long, 4.2, 4, round);
|
||||
|
||||
/* Ceil */
|
||||
TEST_ROUND(double, double, -4.8, -4.0, ceil);
|
||||
TEST_ROUND(double, double, -4.2, -4.0, ceil);
|
||||
TEST_ROUND(double, double, 4.8, 5.0, ceil);
|
||||
TEST_ROUND(double, double, 4.2, 5.0, ceil);
|
||||
|
||||
TEST_ROUND(double, int, -4.8, -4, ceil);
|
||||
TEST_ROUND(double, int, -4.2, -4, ceil);
|
||||
TEST_ROUND(double, int, 4.8, 5, ceil);
|
||||
TEST_ROUND(double, int, 4.2, 5, ceil);
|
||||
|
||||
TEST_ROUND(double, long, -4.8, -4, ceil);
|
||||
TEST_ROUND(double, long, -4.2, -4, ceil);
|
||||
TEST_ROUND(double, long, 4.8, 5, ceil);
|
||||
TEST_ROUND(double, long, 4.2, 5, ceil);
|
||||
|
||||
TEST_ROUND(float, long, -4.8, -4, ceil);
|
||||
TEST_ROUND(float, long, -4.2, -4, ceil);
|
||||
TEST_ROUND(float, long, 4.8, 5, ceil);
|
||||
TEST_ROUND(float, long, 4.2, 5, ceil);
|
||||
|
||||
/* Floor */
|
||||
TEST_ROUND(double, double, -4.8, -5.0, floor);
|
||||
TEST_ROUND(double, double, -4.2, -5.0, floor);
|
||||
TEST_ROUND(double, double, 4.8, 4.0, floor);
|
||||
TEST_ROUND(double, double, 4.2, 4.0, floor);
|
||||
|
||||
TEST_ROUND(double, int, -4.8, -5, floor);
|
||||
TEST_ROUND(double, int, -4.2, -5, floor);
|
||||
TEST_ROUND(double, int, 4.8, 4, floor);
|
||||
TEST_ROUND(double, int, 4.2, 4, floor);
|
||||
|
||||
TEST_ROUND(double, long, -4.8, -5, floor);
|
||||
TEST_ROUND(double, long, -4.2, -5, floor);
|
||||
TEST_ROUND(double, long, 4.8, 4, floor);
|
||||
TEST_ROUND(double, long, 4.2, 4, floor);
|
||||
|
||||
TEST_ROUND(float, long, -4.8, -5, floor);
|
||||
TEST_ROUND(float, long, -4.2, -5, floor);
|
||||
TEST_ROUND(float, long, 4.8, 4, floor);
|
||||
TEST_ROUND(float, long, 4.2, 4, floor);
|
||||
|
||||
/* Trunc */
|
||||
TEST_ROUND(double, double, -4.8, -4.0, trunc);
|
||||
TEST_ROUND(double, double, -4.2, -4.0, trunc);
|
||||
TEST_ROUND(double, double, 4.8, 4.0, trunc);
|
||||
TEST_ROUND(double, double, 4.2, 4.0, trunc);
|
||||
|
||||
TEST_ROUND(double, int, -4.8, -4, trunc);
|
||||
TEST_ROUND(double, int, -4.2, -4, trunc);
|
||||
TEST_ROUND(double, int, 4.8, 4, trunc);
|
||||
TEST_ROUND(double, int, 4.2, 4, trunc);
|
||||
|
||||
TEST_ROUND(double, long, -4.8, -4, trunc);
|
||||
TEST_ROUND(double, long, -4.2, -4, trunc);
|
||||
TEST_ROUND(double, long, 4.8, 4, trunc);
|
||||
TEST_ROUND(double, long, 4.2, 4, trunc);
|
||||
|
||||
TEST_ROUND(float, long, -4.8, -4, trunc);
|
||||
TEST_ROUND(float, long, -4.2, -4, trunc);
|
||||
TEST_ROUND(float, long, 4.8, 4, trunc);
|
||||
TEST_ROUND(float, long, 4.2, 4, trunc);
|
||||
|
||||
/* Nearbyint */
|
||||
TEST_ROUND(double, double, -4.8, -5.0, nearbyint);
|
||||
TEST_ROUND(double, double, -4.2, -4.0, nearbyint);
|
||||
TEST_ROUND(double, double, 4.8, 5.0, nearbyint);
|
||||
TEST_ROUND(double, double, 4.2, 4.0, nearbyint);
|
||||
|
||||
TEST_ROUND(double, int, -4.8, -5, nearbyint);
|
||||
TEST_ROUND(double, int, -4.2, -4, nearbyint);
|
||||
TEST_ROUND(double, int, 4.8, 5, nearbyint);
|
||||
TEST_ROUND(double, int, 4.2, 4, nearbyint);
|
||||
|
||||
TEST_ROUND(double, long, -4.8, -5, nearbyint);
|
||||
TEST_ROUND(double, long, -4.2, -4, nearbyint);
|
||||
TEST_ROUND(double, long, 4.8, 5, nearbyint);
|
||||
TEST_ROUND(double, long, 4.2, 4, nearbyint);
|
||||
|
||||
TEST_ROUND(float, long, -4.8, -5, nearbyint);
|
||||
TEST_ROUND(float, long, -4.2, -4, nearbyint);
|
||||
TEST_ROUND(float, long, 4.8, 5, nearbyint);
|
||||
TEST_ROUND(float, long, 4.2, 4, nearbyint);
|
||||
|
||||
exit(0);
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
/* { dg-do compile { target { riscv32*-*-* } } } */
|
||||
/* { dg-options "-march=rv32gc -mabi=ilp32d -fno-math-errno -funsafe-math-optimizations -fno-inline" } */
|
||||
/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
|
||||
|
||||
#include "round.c"
|
||||
|
||||
/* { dg-final { scan-assembler-times {\mfcvt.w.s} 15 } } */
|
||||
/* { dg-final { scan-assembler-times {\mfcvt.s.w} 5 } } */
|
||||
/* { dg-final { scan-assembler-times {\mfcvt.d.w} 65 } } */
|
||||
/* { dg-final { scan-assembler-times {\mfcvt.w.d} 15 } } */
|
||||
/* { dg-final { scan-assembler-times {,rup} 6 } } */
|
||||
/* { dg-final { scan-assembler-times {,rmm} 6 } } */
|
||||
/* { dg-final { scan-assembler-times {,rdn} 6 } } */
|
||||
/* { dg-final { scan-assembler-times {,rtz} 6 } } */
|
||||
/* { dg-final { scan-assembler-not {\mfcvt.l.d} } } */
|
||||
/* { dg-final { scan-assembler-not {\mfcvt.d.l} } } */
|
||||
/* { dg-final { scan-assembler-not "\\sceil\\s" } } */
|
||||
/* { dg-final { scan-assembler-not "\\sfloor\\s" } } */
|
||||
/* { dg-final { scan-assembler-not "\\sround\\s" } } */
|
||||
/* { dg-final { scan-assembler-not "\\snearbyint\\s" } } */
|
||||
/* { dg-final { scan-assembler-not "\\srint\\s" } } */
|
||||
/* { dg-final { scan-assembler-not "\\stail\\s" } } */
|
||||
|
|
@ -0,0 +1,23 @@
|
|||
/* { dg-do compile { target { riscv64*-*-* } } } */
|
||||
/* { dg-options "-march=rv64gc -mabi=lp64d -fno-math-errno -funsafe-math-optimizations -fno-inline" } */
|
||||
/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
|
||||
|
||||
#include "round.c"
|
||||
|
||||
/* { dg-final { scan-assembler-times {\mfcvt.w.s} 10 } } */
|
||||
/* { dg-final { scan-assembler-times {\mfcvt.s.w} 5 } } */
|
||||
/* { dg-final { scan-assembler-times {\mfcvt.l.d} 10 } } */
|
||||
/* { dg-final { scan-assembler-times {\mfcvt.d.l} 45 } } */
|
||||
/* { dg-final { scan-assembler-times {\mfcvt.w.d} 5 } } */
|
||||
/* { dg-final { scan-assembler-times {,rup} 6 } } */
|
||||
/* { dg-final { scan-assembler-times {,rmm} 6 } } */
|
||||
/* { dg-final { scan-assembler-times {,rdn} 6 } } */
|
||||
/* { dg-final { scan-assembler-times {,rtz} 6 } } */
|
||||
/* { dg-final { scan-assembler-not "\\sceil\\s" } } */
|
||||
/* { dg-final { scan-assembler-not "\\sfloor\\s" } } */
|
||||
/* { dg-final { scan-assembler-not "\\sround\\s" } } */
|
||||
/* { dg-final { scan-assembler-not "\\snearbyint\\s" } } */
|
||||
/* { dg-final { scan-assembler-not "\\srint\\s" } } */
|
||||
/* { dg-final { scan-assembler-not "\\stail\\s" } } */
|
||||
/* { dg-final { scan-assembler-not "\\ssext.w\\s" } } */
|
||||
|
||||
Loading…
Reference in New Issue