crypto: ti - Add driver for DTHE V2 AES Engine (ECB, CBC)
Add support for ECB and CBC modes in the AES Engine of the DTHE V2 hardware cryptography engine. Signed-off-by: T Pratham <t-pratham@ti.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
T Pratham
Herbert Xu
parent
97d37c0a44
commit
52f641bc63
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@ -25174,6 +25174,7 @@ M: T Pratham <t-pratham@ti.com>
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L: linux-crypto@vger.kernel.org
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S: Supported
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F: Documentation/devicetree/bindings/crypto/ti,am62l-dthev2.yaml
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F: drivers/crypto/ti/
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TI DAVINCI MACHINE SUPPORT
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M: Bartosz Golaszewski <brgl@bgdev.pl>
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@ -863,5 +863,6 @@ config CRYPTO_DEV_SA2UL
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source "drivers/crypto/aspeed/Kconfig"
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source "drivers/crypto/starfive/Kconfig"
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source "drivers/crypto/inside-secure/eip93/Kconfig"
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source "drivers/crypto/ti/Kconfig"
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endif # CRYPTO_HW
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@ -48,3 +48,4 @@ obj-$(CONFIG_CRYPTO_DEV_AMLOGIC_GXL) += amlogic/
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obj-y += intel/
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obj-y += starfive/
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obj-y += cavium/
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obj-$(CONFIG_ARCH_K3) += ti/
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@ -0,0 +1,14 @@
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# SPDX-License-Identifier: GPL-2.0-only
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config CRYPTO_DEV_TI_DTHEV2
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tristate "Support for TI DTHE V2 cryptography engine"
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depends on CRYPTO && CRYPTO_HW && ARCH_K3
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select CRYPTO_ENGINE
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select CRYPTO_SKCIPHER
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select CRYPTO_ECB
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select CRYPTO_CBC
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help
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This enables support for the TI DTHE V2 hw cryptography engine
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which can be found on TI K3 SOCs. Selecting this enables use
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of hardware offloading for cryptographic algorithms on
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these devices, providing enhanced resistance against side-channel
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attacks.
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@ -0,0 +1,3 @@
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# SPDX-License-Identifier: GPL-2.0-only
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obj-$(CONFIG_CRYPTO_DEV_TI_DTHEV2) += dthev2.o
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dthev2-objs := dthev2-common.o dthev2-aes.o
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@ -0,0 +1,411 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* K3 DTHE V2 crypto accelerator driver
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*
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* Copyright (C) Texas Instruments 2025 - https://www.ti.com
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* Author: T Pratham <t-pratham@ti.com>
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*/
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#include <crypto/aead.h>
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#include <crypto/aes.h>
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#include <crypto/algapi.h>
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#include <crypto/engine.h>
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#include <crypto/internal/aead.h>
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#include <crypto/internal/skcipher.h>
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#include "dthev2-common.h"
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#include <linux/delay.h>
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#include <linux/dmaengine.h>
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#include <linux/dma-mapping.h>
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#include <linux/io.h>
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#include <linux/scatterlist.h>
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/* Registers */
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// AES Engine
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#define DTHE_P_AES_BASE 0x7000
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#define DTHE_P_AES_KEY1_0 0x0038
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#define DTHE_P_AES_KEY1_1 0x003C
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#define DTHE_P_AES_KEY1_2 0x0030
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#define DTHE_P_AES_KEY1_3 0x0034
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#define DTHE_P_AES_KEY1_4 0x0028
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#define DTHE_P_AES_KEY1_5 0x002C
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#define DTHE_P_AES_KEY1_6 0x0020
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#define DTHE_P_AES_KEY1_7 0x0024
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#define DTHE_P_AES_IV_IN_0 0x0040
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#define DTHE_P_AES_IV_IN_1 0x0044
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#define DTHE_P_AES_IV_IN_2 0x0048
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#define DTHE_P_AES_IV_IN_3 0x004C
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#define DTHE_P_AES_CTRL 0x0050
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#define DTHE_P_AES_C_LENGTH_0 0x0054
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#define DTHE_P_AES_C_LENGTH_1 0x0058
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#define DTHE_P_AES_AUTH_LENGTH 0x005C
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#define DTHE_P_AES_DATA_IN_OUT 0x0060
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#define DTHE_P_AES_SYSCONFIG 0x0084
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#define DTHE_P_AES_IRQSTATUS 0x008C
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#define DTHE_P_AES_IRQENABLE 0x0090
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/* Register write values and macros */
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enum aes_ctrl_mode_masks {
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AES_CTRL_ECB_MASK = 0x00,
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AES_CTRL_CBC_MASK = BIT(5),
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};
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#define DTHE_AES_CTRL_MODE_CLEAR_MASK ~GENMASK(28, 5)
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#define DTHE_AES_CTRL_DIR_ENC BIT(2)
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#define DTHE_AES_CTRL_KEYSIZE_16B BIT(3)
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#define DTHE_AES_CTRL_KEYSIZE_24B BIT(4)
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#define DTHE_AES_CTRL_KEYSIZE_32B (BIT(3) | BIT(4))
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#define DTHE_AES_CTRL_SAVE_CTX_SET BIT(29)
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#define DTHE_AES_CTRL_OUTPUT_READY BIT_MASK(0)
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#define DTHE_AES_CTRL_INPUT_READY BIT_MASK(1)
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#define DTHE_AES_CTRL_SAVED_CTX_READY BIT_MASK(30)
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#define DTHE_AES_CTRL_CTX_READY BIT_MASK(31)
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#define DTHE_AES_SYSCONFIG_DMA_DATA_IN_OUT_EN GENMASK(6, 5)
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#define DTHE_AES_IRQENABLE_EN_ALL GENMASK(3, 0)
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/* Misc */
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#define AES_IV_SIZE AES_BLOCK_SIZE
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#define AES_BLOCK_WORDS (AES_BLOCK_SIZE / sizeof(u32))
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#define AES_IV_WORDS AES_BLOCK_WORDS
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static int dthe_cipher_init_tfm(struct crypto_skcipher *tfm)
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{
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struct dthe_tfm_ctx *ctx = crypto_skcipher_ctx(tfm);
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struct dthe_data *dev_data = dthe_get_dev(ctx);
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ctx->dev_data = dev_data;
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ctx->keylen = 0;
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return 0;
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}
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static int dthe_aes_setkey(struct crypto_skcipher *tfm, const u8 *key, unsigned int keylen)
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{
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struct dthe_tfm_ctx *ctx = crypto_skcipher_ctx(tfm);
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if (keylen != AES_KEYSIZE_128 && keylen != AES_KEYSIZE_192 && keylen != AES_KEYSIZE_256)
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return -EINVAL;
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ctx->keylen = keylen;
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memcpy(ctx->key, key, keylen);
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return 0;
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}
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static int dthe_aes_ecb_setkey(struct crypto_skcipher *tfm, const u8 *key, unsigned int keylen)
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{
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struct dthe_tfm_ctx *ctx = crypto_skcipher_ctx(tfm);
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ctx->aes_mode = DTHE_AES_ECB;
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return dthe_aes_setkey(tfm, key, keylen);
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}
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static int dthe_aes_cbc_setkey(struct crypto_skcipher *tfm, const u8 *key, unsigned int keylen)
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{
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struct dthe_tfm_ctx *ctx = crypto_skcipher_ctx(tfm);
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ctx->aes_mode = DTHE_AES_CBC;
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return dthe_aes_setkey(tfm, key, keylen);
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}
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static void dthe_aes_set_ctrl_key(struct dthe_tfm_ctx *ctx,
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struct dthe_aes_req_ctx *rctx,
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u32 *iv_in)
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{
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struct dthe_data *dev_data = dthe_get_dev(ctx);
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void __iomem *aes_base_reg = dev_data->regs + DTHE_P_AES_BASE;
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u32 ctrl_val = 0;
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writel_relaxed(ctx->key[0], aes_base_reg + DTHE_P_AES_KEY1_0);
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writel_relaxed(ctx->key[1], aes_base_reg + DTHE_P_AES_KEY1_1);
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writel_relaxed(ctx->key[2], aes_base_reg + DTHE_P_AES_KEY1_2);
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writel_relaxed(ctx->key[3], aes_base_reg + DTHE_P_AES_KEY1_3);
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if (ctx->keylen > AES_KEYSIZE_128) {
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writel_relaxed(ctx->key[4], aes_base_reg + DTHE_P_AES_KEY1_4);
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writel_relaxed(ctx->key[5], aes_base_reg + DTHE_P_AES_KEY1_5);
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}
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if (ctx->keylen == AES_KEYSIZE_256) {
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writel_relaxed(ctx->key[6], aes_base_reg + DTHE_P_AES_KEY1_6);
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writel_relaxed(ctx->key[7], aes_base_reg + DTHE_P_AES_KEY1_7);
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}
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if (rctx->enc)
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ctrl_val |= DTHE_AES_CTRL_DIR_ENC;
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if (ctx->keylen == AES_KEYSIZE_128)
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ctrl_val |= DTHE_AES_CTRL_KEYSIZE_16B;
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else if (ctx->keylen == AES_KEYSIZE_192)
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ctrl_val |= DTHE_AES_CTRL_KEYSIZE_24B;
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else
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ctrl_val |= DTHE_AES_CTRL_KEYSIZE_32B;
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// Write AES mode
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ctrl_val &= DTHE_AES_CTRL_MODE_CLEAR_MASK;
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switch (ctx->aes_mode) {
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case DTHE_AES_ECB:
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ctrl_val |= AES_CTRL_ECB_MASK;
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break;
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case DTHE_AES_CBC:
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ctrl_val |= AES_CTRL_CBC_MASK;
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break;
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}
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if (iv_in) {
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ctrl_val |= DTHE_AES_CTRL_SAVE_CTX_SET;
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for (int i = 0; i < AES_IV_WORDS; ++i)
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writel_relaxed(iv_in[i],
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aes_base_reg + DTHE_P_AES_IV_IN_0 + (DTHE_REG_SIZE * i));
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}
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writel_relaxed(ctrl_val, aes_base_reg + DTHE_P_AES_CTRL);
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}
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static void dthe_aes_dma_in_callback(void *data)
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{
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struct skcipher_request *req = (struct skcipher_request *)data;
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struct dthe_aes_req_ctx *rctx = skcipher_request_ctx(req);
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complete(&rctx->aes_compl);
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}
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static int dthe_aes_run(struct crypto_engine *engine, void *areq)
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{
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struct skcipher_request *req = container_of(areq, struct skcipher_request, base);
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struct dthe_tfm_ctx *ctx = crypto_skcipher_ctx(crypto_skcipher_reqtfm(req));
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struct dthe_data *dev_data = dthe_get_dev(ctx);
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struct dthe_aes_req_ctx *rctx = skcipher_request_ctx(req);
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unsigned int len = req->cryptlen;
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struct scatterlist *src = req->src;
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struct scatterlist *dst = req->dst;
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int src_nents = sg_nents_for_len(src, len);
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int dst_nents;
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int src_mapped_nents;
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int dst_mapped_nents;
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bool diff_dst;
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enum dma_data_direction src_dir, dst_dir;
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struct device *tx_dev, *rx_dev;
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struct dma_async_tx_descriptor *desc_in, *desc_out;
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int ret;
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void __iomem *aes_base_reg = dev_data->regs + DTHE_P_AES_BASE;
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u32 aes_irqenable_val = readl_relaxed(aes_base_reg + DTHE_P_AES_IRQENABLE);
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u32 aes_sysconfig_val = readl_relaxed(aes_base_reg + DTHE_P_AES_SYSCONFIG);
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aes_sysconfig_val |= DTHE_AES_SYSCONFIG_DMA_DATA_IN_OUT_EN;
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writel_relaxed(aes_sysconfig_val, aes_base_reg + DTHE_P_AES_SYSCONFIG);
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aes_irqenable_val |= DTHE_AES_IRQENABLE_EN_ALL;
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writel_relaxed(aes_irqenable_val, aes_base_reg + DTHE_P_AES_IRQENABLE);
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if (src == dst) {
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diff_dst = false;
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src_dir = DMA_BIDIRECTIONAL;
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dst_dir = DMA_BIDIRECTIONAL;
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} else {
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diff_dst = true;
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src_dir = DMA_TO_DEVICE;
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dst_dir = DMA_FROM_DEVICE;
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}
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tx_dev = dmaengine_get_dma_device(dev_data->dma_aes_tx);
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rx_dev = dmaengine_get_dma_device(dev_data->dma_aes_rx);
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src_mapped_nents = dma_map_sg(tx_dev, src, src_nents, src_dir);
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if (src_mapped_nents == 0) {
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ret = -EINVAL;
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goto aes_err;
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}
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if (!diff_dst) {
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dst_nents = src_nents;
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dst_mapped_nents = src_mapped_nents;
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} else {
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dst_nents = sg_nents_for_len(dst, len);
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dst_mapped_nents = dma_map_sg(rx_dev, dst, dst_nents, dst_dir);
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if (dst_mapped_nents == 0) {
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dma_unmap_sg(tx_dev, src, src_nents, src_dir);
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ret = -EINVAL;
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goto aes_err;
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}
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}
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desc_in = dmaengine_prep_slave_sg(dev_data->dma_aes_rx, dst, dst_mapped_nents,
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DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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if (!desc_in) {
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dev_err(dev_data->dev, "IN prep_slave_sg() failed\n");
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ret = -EINVAL;
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goto aes_prep_err;
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}
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desc_out = dmaengine_prep_slave_sg(dev_data->dma_aes_tx, src, src_mapped_nents,
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DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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if (!desc_out) {
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dev_err(dev_data->dev, "OUT prep_slave_sg() failed\n");
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ret = -EINVAL;
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goto aes_prep_err;
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}
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desc_in->callback = dthe_aes_dma_in_callback;
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desc_in->callback_param = req;
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init_completion(&rctx->aes_compl);
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if (ctx->aes_mode == DTHE_AES_ECB)
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dthe_aes_set_ctrl_key(ctx, rctx, NULL);
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else
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dthe_aes_set_ctrl_key(ctx, rctx, (u32 *)req->iv);
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writel_relaxed(lower_32_bits(req->cryptlen), aes_base_reg + DTHE_P_AES_C_LENGTH_0);
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writel_relaxed(upper_32_bits(req->cryptlen), aes_base_reg + DTHE_P_AES_C_LENGTH_1);
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dmaengine_submit(desc_in);
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dmaengine_submit(desc_out);
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dma_async_issue_pending(dev_data->dma_aes_rx);
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dma_async_issue_pending(dev_data->dma_aes_tx);
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// Need to do a timeout to ensure finalise gets called if DMA callback fails for any reason
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ret = wait_for_completion_timeout(&rctx->aes_compl, msecs_to_jiffies(DTHE_DMA_TIMEOUT_MS));
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if (!ret) {
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ret = -ETIMEDOUT;
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dmaengine_terminate_sync(dev_data->dma_aes_rx);
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dmaengine_terminate_sync(dev_data->dma_aes_tx);
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for (int i = 0; i < AES_BLOCK_WORDS; ++i)
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readl_relaxed(aes_base_reg + DTHE_P_AES_DATA_IN_OUT + (DTHE_REG_SIZE * i));
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} else {
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ret = 0;
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}
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// For modes other than ECB, read IV_OUT
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if (ctx->aes_mode != DTHE_AES_ECB) {
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u32 *iv_out = (u32 *)req->iv;
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for (int i = 0; i < AES_IV_WORDS; ++i)
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iv_out[i] = readl_relaxed(aes_base_reg +
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DTHE_P_AES_IV_IN_0 +
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(DTHE_REG_SIZE * i));
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}
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aes_prep_err:
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dma_unmap_sg(tx_dev, src, src_nents, src_dir);
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if (dst_dir != DMA_BIDIRECTIONAL)
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dma_unmap_sg(rx_dev, dst, dst_nents, dst_dir);
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aes_err:
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local_bh_disable();
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crypto_finalize_skcipher_request(dev_data->engine, req, ret);
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local_bh_enable();
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return ret;
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}
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static int dthe_aes_crypt(struct skcipher_request *req)
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{
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struct dthe_tfm_ctx *ctx = crypto_skcipher_ctx(crypto_skcipher_reqtfm(req));
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struct dthe_data *dev_data = dthe_get_dev(ctx);
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struct crypto_engine *engine;
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/*
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* If data is not a multiple of AES_BLOCK_SIZE, need to return -EINVAL
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* If data length input is zero, no need to do any operation.
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*/
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if (req->cryptlen % AES_BLOCK_SIZE)
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return -EINVAL;
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if (req->cryptlen == 0)
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return 0;
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engine = dev_data->engine;
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return crypto_transfer_skcipher_request_to_engine(engine, req);
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}
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static int dthe_aes_encrypt(struct skcipher_request *req)
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{
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struct dthe_aes_req_ctx *rctx = skcipher_request_ctx(req);
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rctx->enc = 1;
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return dthe_aes_crypt(req);
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}
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static int dthe_aes_decrypt(struct skcipher_request *req)
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{
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struct dthe_aes_req_ctx *rctx = skcipher_request_ctx(req);
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rctx->enc = 0;
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return dthe_aes_crypt(req);
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}
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static struct skcipher_engine_alg cipher_algs[] = {
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{
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.base.init = dthe_cipher_init_tfm,
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.base.setkey = dthe_aes_ecb_setkey,
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.base.encrypt = dthe_aes_encrypt,
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.base.decrypt = dthe_aes_decrypt,
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.base.min_keysize = AES_MIN_KEY_SIZE,
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.base.max_keysize = AES_MAX_KEY_SIZE,
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.base.base = {
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.cra_name = "ecb(aes)",
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.cra_driver_name = "ecb-aes-dthev2",
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.cra_priority = 299,
|
||||
.cra_flags = CRYPTO_ALG_TYPE_SKCIPHER |
|
||||
CRYPTO_ALG_KERN_DRIVER_ONLY,
|
||||
.cra_alignmask = AES_BLOCK_SIZE - 1,
|
||||
.cra_blocksize = AES_BLOCK_SIZE,
|
||||
.cra_ctxsize = sizeof(struct dthe_tfm_ctx),
|
||||
.cra_reqsize = sizeof(struct dthe_aes_req_ctx),
|
||||
.cra_module = THIS_MODULE,
|
||||
},
|
||||
.op.do_one_request = dthe_aes_run,
|
||||
}, /* ECB AES */
|
||||
{
|
||||
.base.init = dthe_cipher_init_tfm,
|
||||
.base.setkey = dthe_aes_cbc_setkey,
|
||||
.base.encrypt = dthe_aes_encrypt,
|
||||
.base.decrypt = dthe_aes_decrypt,
|
||||
.base.min_keysize = AES_MIN_KEY_SIZE,
|
||||
.base.max_keysize = AES_MAX_KEY_SIZE,
|
||||
.base.ivsize = AES_IV_SIZE,
|
||||
.base.base = {
|
||||
.cra_name = "cbc(aes)",
|
||||
.cra_driver_name = "cbc-aes-dthev2",
|
||||
.cra_priority = 299,
|
||||
.cra_flags = CRYPTO_ALG_TYPE_SKCIPHER |
|
||||
CRYPTO_ALG_KERN_DRIVER_ONLY,
|
||||
.cra_alignmask = AES_BLOCK_SIZE - 1,
|
||||
.cra_blocksize = AES_BLOCK_SIZE,
|
||||
.cra_ctxsize = sizeof(struct dthe_tfm_ctx),
|
||||
.cra_reqsize = sizeof(struct dthe_aes_req_ctx),
|
||||
.cra_module = THIS_MODULE,
|
||||
},
|
||||
.op.do_one_request = dthe_aes_run,
|
||||
} /* CBC AES */
|
||||
};
|
||||
|
||||
int dthe_register_aes_algs(void)
|
||||
{
|
||||
return crypto_engine_register_skciphers(cipher_algs, ARRAY_SIZE(cipher_algs));
|
||||
}
|
||||
|
||||
void dthe_unregister_aes_algs(void)
|
||||
{
|
||||
crypto_engine_unregister_skciphers(cipher_algs, ARRAY_SIZE(cipher_algs));
|
||||
}
|
||||
|
|
@ -0,0 +1,217 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* K3 DTHE V2 crypto accelerator driver
|
||||
*
|
||||
* Copyright (C) Texas Instruments 2025 - https://www.ti.com
|
||||
* Author: T Pratham <t-pratham@ti.com>
|
||||
*/
|
||||
|
||||
#include <crypto/aes.h>
|
||||
#include <crypto/algapi.h>
|
||||
#include <crypto/engine.h>
|
||||
#include <crypto/internal/aead.h>
|
||||
#include <crypto/internal/skcipher.h>
|
||||
|
||||
#include "dthev2-common.h"
|
||||
|
||||
#include <linux/delay.h>
|
||||
#include <linux/dmaengine.h>
|
||||
#include <linux/dmapool.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/mod_devicetable.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/scatterlist.h>
|
||||
|
||||
#define DRIVER_NAME "dthev2"
|
||||
|
||||
static struct dthe_list dthe_dev_list = {
|
||||
.dev_list = LIST_HEAD_INIT(dthe_dev_list.dev_list),
|
||||
.lock = __SPIN_LOCK_UNLOCKED(dthe_dev_list.lock),
|
||||
};
|
||||
|
||||
struct dthe_data *dthe_get_dev(struct dthe_tfm_ctx *ctx)
|
||||
{
|
||||
struct dthe_data *dev_data;
|
||||
|
||||
if (ctx->dev_data)
|
||||
return ctx->dev_data;
|
||||
|
||||
spin_lock_bh(&dthe_dev_list.lock);
|
||||
dev_data = list_first_entry(&dthe_dev_list.dev_list, struct dthe_data, list);
|
||||
if (dev_data)
|
||||
list_move_tail(&dev_data->list, &dthe_dev_list.dev_list);
|
||||
spin_unlock_bh(&dthe_dev_list.lock);
|
||||
|
||||
return dev_data;
|
||||
}
|
||||
|
||||
static int dthe_dma_init(struct dthe_data *dev_data)
|
||||
{
|
||||
int ret;
|
||||
struct dma_slave_config cfg;
|
||||
|
||||
dev_data->dma_aes_rx = NULL;
|
||||
dev_data->dma_aes_tx = NULL;
|
||||
dev_data->dma_sha_tx = NULL;
|
||||
|
||||
dev_data->dma_aes_rx = dma_request_chan(dev_data->dev, "rx");
|
||||
if (IS_ERR(dev_data->dma_aes_rx)) {
|
||||
return dev_err_probe(dev_data->dev, PTR_ERR(dev_data->dma_aes_rx),
|
||||
"Unable to request rx DMA channel\n");
|
||||
}
|
||||
|
||||
dev_data->dma_aes_tx = dma_request_chan(dev_data->dev, "tx1");
|
||||
if (IS_ERR(dev_data->dma_aes_tx)) {
|
||||
ret = dev_err_probe(dev_data->dev, PTR_ERR(dev_data->dma_aes_tx),
|
||||
"Unable to request tx1 DMA channel\n");
|
||||
goto err_dma_aes_tx;
|
||||
}
|
||||
|
||||
dev_data->dma_sha_tx = dma_request_chan(dev_data->dev, "tx2");
|
||||
if (IS_ERR(dev_data->dma_sha_tx)) {
|
||||
ret = dev_err_probe(dev_data->dev, PTR_ERR(dev_data->dma_sha_tx),
|
||||
"Unable to request tx2 DMA channel\n");
|
||||
goto err_dma_sha_tx;
|
||||
}
|
||||
|
||||
memzero_explicit(&cfg, sizeof(cfg));
|
||||
|
||||
cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
|
||||
cfg.src_maxburst = 4;
|
||||
|
||||
ret = dmaengine_slave_config(dev_data->dma_aes_rx, &cfg);
|
||||
if (ret) {
|
||||
dev_err(dev_data->dev, "Can't configure IN dmaengine slave: %d\n", ret);
|
||||
goto err_dma_config;
|
||||
}
|
||||
|
||||
cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
|
||||
cfg.dst_maxburst = 4;
|
||||
|
||||
ret = dmaengine_slave_config(dev_data->dma_aes_tx, &cfg);
|
||||
if (ret) {
|
||||
dev_err(dev_data->dev, "Can't configure OUT dmaengine slave: %d\n", ret);
|
||||
goto err_dma_config;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
err_dma_config:
|
||||
dma_release_channel(dev_data->dma_sha_tx);
|
||||
err_dma_sha_tx:
|
||||
dma_release_channel(dev_data->dma_aes_tx);
|
||||
err_dma_aes_tx:
|
||||
dma_release_channel(dev_data->dma_aes_rx);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int dthe_register_algs(void)
|
||||
{
|
||||
return dthe_register_aes_algs();
|
||||
}
|
||||
|
||||
static void dthe_unregister_algs(void)
|
||||
{
|
||||
dthe_unregister_aes_algs();
|
||||
}
|
||||
|
||||
static int dthe_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct dthe_data *dev_data;
|
||||
int ret;
|
||||
|
||||
dev_data = devm_kzalloc(dev, sizeof(*dev_data), GFP_KERNEL);
|
||||
if (!dev_data)
|
||||
return -ENOMEM;
|
||||
|
||||
dev_data->dev = dev;
|
||||
dev_data->regs = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(dev_data->regs))
|
||||
return PTR_ERR(dev_data->regs);
|
||||
|
||||
platform_set_drvdata(pdev, dev_data);
|
||||
|
||||
spin_lock(&dthe_dev_list.lock);
|
||||
list_add(&dev_data->list, &dthe_dev_list.dev_list);
|
||||
spin_unlock(&dthe_dev_list.lock);
|
||||
|
||||
ret = dthe_dma_init(dev_data);
|
||||
if (ret)
|
||||
goto probe_dma_err;
|
||||
|
||||
dev_data->engine = crypto_engine_alloc_init(dev, 1);
|
||||
if (!dev_data->engine) {
|
||||
ret = -ENOMEM;
|
||||
goto probe_engine_err;
|
||||
}
|
||||
|
||||
ret = crypto_engine_start(dev_data->engine);
|
||||
if (ret) {
|
||||
dev_err(dev, "Failed to start crypto engine\n");
|
||||
goto probe_engine_start_err;
|
||||
}
|
||||
|
||||
ret = dthe_register_algs();
|
||||
if (ret) {
|
||||
dev_err(dev, "Failed to register algs\n");
|
||||
goto probe_engine_start_err;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
probe_engine_start_err:
|
||||
crypto_engine_exit(dev_data->engine);
|
||||
probe_engine_err:
|
||||
dma_release_channel(dev_data->dma_aes_rx);
|
||||
dma_release_channel(dev_data->dma_aes_tx);
|
||||
dma_release_channel(dev_data->dma_sha_tx);
|
||||
probe_dma_err:
|
||||
spin_lock(&dthe_dev_list.lock);
|
||||
list_del(&dev_data->list);
|
||||
spin_unlock(&dthe_dev_list.lock);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void dthe_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct dthe_data *dev_data = platform_get_drvdata(pdev);
|
||||
|
||||
spin_lock(&dthe_dev_list.lock);
|
||||
list_del(&dev_data->list);
|
||||
spin_unlock(&dthe_dev_list.lock);
|
||||
|
||||
dthe_unregister_algs();
|
||||
|
||||
crypto_engine_exit(dev_data->engine);
|
||||
|
||||
dma_release_channel(dev_data->dma_aes_rx);
|
||||
dma_release_channel(dev_data->dma_aes_tx);
|
||||
dma_release_channel(dev_data->dma_sha_tx);
|
||||
}
|
||||
|
||||
static const struct of_device_id dthe_of_match[] = {
|
||||
{ .compatible = "ti,am62l-dthev2", },
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, dthe_of_match);
|
||||
|
||||
static struct platform_driver dthe_driver = {
|
||||
.probe = dthe_probe,
|
||||
.remove = dthe_remove,
|
||||
.driver = {
|
||||
.name = DRIVER_NAME,
|
||||
.of_match_table = dthe_of_match,
|
||||
},
|
||||
};
|
||||
|
||||
module_platform_driver(dthe_driver);
|
||||
|
||||
MODULE_AUTHOR("T Pratham <t-pratham@ti.com>");
|
||||
MODULE_DESCRIPTION("Texas Instruments DTHE V2 driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
|
|
@ -0,0 +1,101 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* K3 DTHE V2 crypto accelerator driver
|
||||
*
|
||||
* Copyright (C) Texas Instruments 2025 - https://www.ti.com
|
||||
* Author: T Pratham <t-pratham@ti.com>
|
||||
*/
|
||||
|
||||
#ifndef __TI_DTHEV2_H__
|
||||
#define __TI_DTHEV2_H__
|
||||
|
||||
#include <crypto/aead.h>
|
||||
#include <crypto/aes.h>
|
||||
#include <crypto/algapi.h>
|
||||
#include <crypto/engine.h>
|
||||
#include <crypto/hash.h>
|
||||
#include <crypto/internal/aead.h>
|
||||
#include <crypto/internal/hash.h>
|
||||
#include <crypto/internal/skcipher.h>
|
||||
|
||||
#include <linux/delay.h>
|
||||
#include <linux/dmaengine.h>
|
||||
#include <linux/dmapool.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/scatterlist.h>
|
||||
|
||||
#define DTHE_REG_SIZE 4
|
||||
#define DTHE_DMA_TIMEOUT_MS 2000
|
||||
|
||||
enum dthe_aes_mode {
|
||||
DTHE_AES_ECB = 0,
|
||||
DTHE_AES_CBC,
|
||||
};
|
||||
|
||||
/* Driver specific struct definitions */
|
||||
|
||||
/**
|
||||
* struct dthe_data - DTHE_V2 driver instance data
|
||||
* @dev: Device pointer
|
||||
* @regs: Base address of the register space
|
||||
* @list: list node for dev
|
||||
* @engine: Crypto engine instance
|
||||
* @dma_aes_rx: AES Rx DMA Channel
|
||||
* @dma_aes_tx: AES Tx DMA Channel
|
||||
* @dma_sha_tx: SHA Tx DMA Channel
|
||||
*/
|
||||
struct dthe_data {
|
||||
struct device *dev;
|
||||
void __iomem *regs;
|
||||
struct list_head list;
|
||||
struct crypto_engine *engine;
|
||||
|
||||
struct dma_chan *dma_aes_rx;
|
||||
struct dma_chan *dma_aes_tx;
|
||||
|
||||
struct dma_chan *dma_sha_tx;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct dthe_list - device data list head
|
||||
* @dev_list: linked list head
|
||||
* @lock: Spinlock protecting accesses to the list
|
||||
*/
|
||||
struct dthe_list {
|
||||
struct list_head dev_list;
|
||||
spinlock_t lock;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct dthe_tfm_ctx - Transform ctx struct containing ctx for all sub-components of DTHE V2
|
||||
* @dev_data: Device data struct pointer
|
||||
* @keylen: AES key length
|
||||
* @key: AES key
|
||||
* @aes_mode: AES mode
|
||||
*/
|
||||
struct dthe_tfm_ctx {
|
||||
struct dthe_data *dev_data;
|
||||
unsigned int keylen;
|
||||
u32 key[AES_KEYSIZE_256 / sizeof(u32)];
|
||||
enum dthe_aes_mode aes_mode;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct dthe_aes_req_ctx - AES engine req ctx struct
|
||||
* @enc: flag indicating encryption or decryption operation
|
||||
* @aes_compl: Completion variable for use in manual completion in case of DMA callback failure
|
||||
*/
|
||||
struct dthe_aes_req_ctx {
|
||||
int enc;
|
||||
struct completion aes_compl;
|
||||
};
|
||||
|
||||
/* Struct definitions end */
|
||||
|
||||
struct dthe_data *dthe_get_dev(struct dthe_tfm_ctx *ctx);
|
||||
|
||||
int dthe_register_aes_algs(void);
|
||||
void dthe_unregister_aes_algs(void);
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue