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parisc: Convert to generic clockevents 

Convert parisc timer code to generic clockevents framework.

Signed-off-by: Helge Deller <deller@gmx.de>
This commit is contained in:
Helge Deller 2024-08-31 14:26:53 +02:00
parent 75df38aaf1
commit b5ff52be89
4 changed files with 103 additions and 154 deletions
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2
arch/parisc/Kconfig
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@ -72,7 +72,7 @@ config PARISC
select GENERIC_SCHED_CLOCK select GENERIC_SCHED_CLOCK
select GENERIC_IRQ_MIGRATION if SMP select GENERIC_IRQ_MIGRATION if SMP
select HAVE_UNSTABLE_SCHED_CLOCK if SMP select HAVE_UNSTABLE_SCHED_CLOCK if SMP
select LEGACY_TIMER_TICK select GENERIC_CLOCKEVENTS
select CPU_NO_EFFICIENT_FFS select CPU_NO_EFFICIENT_FFS
select THREAD_INFO_IN_TASK select THREAD_INFO_IN_TASK
select NEED_DMA_MAP_STATE select NEED_DMA_MAP_STATE

2
arch/parisc/include/asm/processor.h
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@ -298,7 +298,7 @@ extern unsigned int toc_handler_csum;
extern void do_cpu_irq_mask(struct pt_regs *); extern void do_cpu_irq_mask(struct pt_regs *);
extern irqreturn_t timer_interrupt(int, void *); extern irqreturn_t timer_interrupt(int, void *);
extern irqreturn_t ipi_interrupt(int, void *); extern irqreturn_t ipi_interrupt(int, void *);
extern void start_cpu_itimer(void); extern void parisc_clockevent_init(void);
extern void handle_interruption(int, struct pt_regs *); extern void handle_interruption(int, struct pt_regs *);
/* called from assembly code: */ /* called from assembly code: */

2
arch/parisc/kernel/smp.c
View File

@ -297,7 +297,7 @@ smp_cpu_init(int cpunum)
enter_lazy_tlb(&init_mm, current); enter_lazy_tlb(&init_mm, current);
init_IRQ(); /* make sure no IRQs are enabled or pending */ init_IRQ(); /* make sure no IRQs are enabled or pending */
start_cpu_itimer(); parisc_clockevent_init();
} }

251
arch/parisc/kernel/time.c
View File

@ -1,126 +1,105 @@
// SPDX-License-Identifier: GPL-2.0 // SPDX-License-Identifier: GPL-2.0
/* /*
* linux/arch/parisc/kernel/time.c * Common time service routines for parisc machines.
* based on arch/loongarch/kernel/time.c
* *
* Copyright (C) 1991, 1992, 1995 Linus Torvalds * Copyright (C) 2024 Helge Deller <deller@gmx.de>
* Modifications for ARM (C) 1994, 1995, 1996,1997 Russell King
* Copyright (C) 1999 SuSE GmbH, (Philipp Rumpf, prumpf@tux.org)
*
* 1994-07-02 Alan Modra
* fixed set_rtc_mmss, fixed time.year for >= 2000, new mktime
* 1998-12-20 Updated NTP code according to technical memorandum Jan '96
* "A Kernel Model for Precision Timekeeping" by Dave Mills
*/ */
#include <linux/errno.h> #include <linux/clockchips.h>
#include <linux/module.h> #include <linux/delay.h>
#include <linux/rtc.h> #include <linux/export.h>
#include <linux/sched.h>
#include <linux/sched/clock.h>
#include <linux/sched_clock.h>
#include <linux/kernel.h>
#include <linux/param.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/interrupt.h>
#include <linux/time.h>
#include <linux/init.h> #include <linux/init.h>
#include <linux/smp.h> #include <linux/interrupt.h>
#include <linux/profile.h> #include <linux/kernel.h>
#include <linux/clocksource.h> #include <linux/sched_clock.h>
#include <linux/spinlock.h>
#include <linux/rtc.h>
#include <linux/platform_device.h> #include <linux/platform_device.h>
#include <linux/ftrace.h> #include <asm/processor.h>
#include <linux/uaccess.h> static u64 cr16_clock_freq;
#include <asm/io.h> static unsigned long clocktick;
#include <asm/irq.h>
#include <asm/page.h>
#include <asm/param.h>
#include <asm/pdc.h>
#include <asm/led.h>
#include <linux/timex.h> int time_keeper_id; /* CPU used for timekeeping */
int time_keeper_id __read_mostly; /* CPU used for timekeeping. */ static DEFINE_PER_CPU(struct clock_event_device, parisc_clockevent_device);
static unsigned long clocktick __ro_after_init; /* timer cycles per tick */ static void parisc_event_handler(struct clock_event_device *dev)
/*
* We keep time on PA-RISC Linux by using the Interval Timer which is
* a pair of registers; one is read-only and one is write-only; both
* accessed through CR16. The read-only register is 32 or 64 bits wide,
* and increments by 1 every CPU clock tick. The architecture only
* guarantees us a rate between 0.5 and 2, but all implementations use a
* rate of 1. The write-only register is 32-bits wide. When the lowest
* 32 bits of the read-only register compare equal to the write-only
* register, it raises a maskable external interrupt. Each processor has
* an Interval Timer of its own and they are not synchronised.
*
* We want to generate an interrupt every 1/HZ seconds. So we program
* CR16 to interrupt every @clocktick cycles. The it_value in cpu_data
* is programmed with the intended time of the next tick. We can be
* held off for an arbitrarily long period of time by interrupts being
* disabled, so we may miss one or more ticks.
*/
irqreturn_t __irq_entry timer_interrupt(int irq, void *dev_id)
{ {
unsigned long now; }
unsigned long next_tick;
unsigned long ticks_elapsed = 0;
unsigned int cpu = smp_processor_id();
struct cpuinfo_parisc *cpuinfo = &per_cpu(cpu_data, cpu);
/* gcc can optimize for "read-only" case with a local clocktick */ static int parisc_timer_next_event(unsigned long delta, struct clock_event_device *evt)
unsigned long cpt = clocktick; {
unsigned long new_cr16;
/* Initialize next_tick to the old expected tick time. */ new_cr16 = mfctl(16) + delta;
next_tick = cpuinfo->it_value; mtctl(new_cr16, 16);
/* Calculate how many ticks have elapsed. */ return 0;
now = mfctl(16); }
do {
++ticks_elapsed;
next_tick += cpt;
} while (next_tick - now > cpt);
/* Store (in CR16 cycles) up to when we are accounting right now. */ irqreturn_t timer_interrupt(int irq, void *data)
cpuinfo->it_value = next_tick; {
struct clock_event_device *cd;
int cpu = smp_processor_id();
/* Go do system house keeping. */ cd = &per_cpu(parisc_clockevent_device, cpu);
if (IS_ENABLED(CONFIG_SMP) && (cpu != time_keeper_id))
ticks_elapsed = 0;
legacy_timer_tick(ticks_elapsed);
/* Skip clockticks on purpose if we know we would miss those. if (clockevent_state_periodic(cd))
* The new CR16 must be "later" than current CR16 otherwise parisc_timer_next_event(clocktick, cd);
* itimer would not fire until CR16 wrapped - e.g 4 seconds
* later on a 1Ghz processor. We'll account for the missed
* ticks on the next timer interrupt.
* We want IT to fire modulo clocktick even if we miss/skip some.
* But those interrupts don't in fact get delivered that regularly.
*
* "next_tick - now" will always give the difference regardless
* if one or the other wrapped. If "now" is "bigger" we'll end up
* with a very large unsigned number.
*/
now = mfctl(16);
while (next_tick - now > cpt)
next_tick += cpt;
/* Program the IT when to deliver the next interrupt. if (clockevent_state_periodic(cd) || clockevent_state_oneshot(cd))
* Only bottom 32-bits of next_tick are writable in CR16! cd->event_handler(cd);
* Timer interrupt will be delivered at least a few hundred cycles
* after the IT fires, so if we are too close (<= 8000 cycles) to the
* next cycle, simply skip it.
*/
if (next_tick - now <= 8000)
next_tick += cpt;
mtctl(next_tick, 16);
return IRQ_HANDLED; return IRQ_HANDLED;
} }
static int parisc_set_state_oneshot(struct clock_event_device *evt)
{
parisc_timer_next_event(clocktick, evt);
unsigned long profile_pc(struct pt_regs *regs) return 0;
}
static int parisc_set_state_periodic(struct clock_event_device *evt)
{
parisc_timer_next_event(clocktick, evt);
return 0;
}
static int parisc_set_state_shutdown(struct clock_event_device *evt)
{
return 0;
}
void parisc_clockevent_init(void)
{
unsigned int cpu = smp_processor_id();
unsigned long min_delta = 0x600; /* XXX */
unsigned long max_delta = (1UL << (BITS_PER_LONG - 1));
struct clock_event_device *cd;
cd = &per_cpu(parisc_clockevent_device, cpu);
cd->name = "cr16_clockevent";
cd->features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC |
CLOCK_EVT_FEAT_PERCPU;
cd->irq = TIMER_IRQ;
cd->rating = 320;
cd->cpumask = cpumask_of(cpu);
cd->set_state_oneshot = parisc_set_state_oneshot;
cd->set_state_oneshot_stopped = parisc_set_state_shutdown;
cd->set_state_periodic = parisc_set_state_periodic;
cd->set_state_shutdown = parisc_set_state_shutdown;
cd->set_next_event = parisc_timer_next_event;
cd->event_handler = parisc_event_handler;
clockevents_config_and_register(cd, cr16_clock_freq, min_delta, max_delta);
}
unsigned long notrace profile_pc(struct pt_regs *regs)
{ {
unsigned long pc = instruction_pointer(regs); unsigned long pc = instruction_pointer(regs);
@ -136,32 +115,6 @@ unsigned long profile_pc(struct pt_regs *regs)
} }
EXPORT_SYMBOL(profile_pc); EXPORT_SYMBOL(profile_pc);
/* clock source code */
static u64 notrace read_cr16(struct clocksource *cs)
{
return get_cycles();
}
static struct clocksource clocksource_cr16 = {
.name = "cr16",
.rating = 300,
.read = read_cr16,
.mask = CLOCKSOURCE_MASK(BITS_PER_LONG),
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
};
void start_cpu_itimer(void)
{
unsigned int cpu = smp_processor_id();
unsigned long next_tick = mfctl(16) + clocktick;
mtctl(next_tick, 16); /* kick off Interval Timer (CR16) */
per_cpu(cpu_data, cpu).it_value = next_tick;
}
#if IS_ENABLED(CONFIG_RTC_DRV_GENERIC) #if IS_ENABLED(CONFIG_RTC_DRV_GENERIC)
static int rtc_generic_get_time(struct device *dev, struct rtc_time *tm) static int rtc_generic_get_time(struct device *dev, struct rtc_time *tm)
{ {
@ -224,12 +177,27 @@ void read_persistent_clock64(struct timespec64 *ts)
} }
} }
static u64 notrace read_cr16_sched_clock(void) static u64 notrace read_cr16_sched_clock(void)
{ {
return get_cycles(); return get_cycles();
} }
static u64 notrace read_cr16(struct clocksource *cs)
{
return get_cycles();
}
static struct clocksource clocksource_cr16 = {
.name = "cr16",
.rating = 300,
.read = read_cr16,
.mask = CLOCKSOURCE_MASK(BITS_PER_LONG),
.flags = CLOCK_SOURCE_IS_CONTINUOUS |
CLOCK_SOURCE_VALID_FOR_HRES |
CLOCK_SOURCE_MUST_VERIFY |
CLOCK_SOURCE_VERIFY_PERCPU,
};
/* /*
* timer interrupt and sched_clock() initialization * timer interrupt and sched_clock() initialization
@ -237,33 +205,14 @@ static u64 notrace read_cr16_sched_clock(void)
void __init time_init(void) void __init time_init(void)
{ {
unsigned long cr16_hz; cr16_clock_freq = 100 * PAGE0->mem_10msec; /* Hz */
clocktick = cr16_clock_freq / HZ;
clocktick = (100 * PAGE0->mem_10msec) / HZ;
start_cpu_itimer(); /* get CPU 0 started */
cr16_hz = 100 * PAGE0->mem_10msec; /* Hz */
/* register as sched_clock source */ /* register as sched_clock source */
sched_clock_register(read_cr16_sched_clock, BITS_PER_LONG, cr16_hz); sched_clock_register(read_cr16_sched_clock, BITS_PER_LONG, cr16_clock_freq);
}
static int __init init_cr16_clocksource(void) parisc_clockevent_init();
{
/*
* The cr16 interval timers are not synchronized across CPUs.
*/
if (num_online_cpus() > 1 && !running_on_qemu) {
clocksource_cr16.name = "cr16_unstable";
clocksource_cr16.flags = CLOCK_SOURCE_UNSTABLE;
clocksource_cr16.rating = 0;
}
/* register at clocksource framework */ /* register at clocksource framework */
clocksource_register_hz(&clocksource_cr16, clocksource_register_hz(&clocksource_cr16, cr16_clock_freq);
100 * PAGE0->mem_10msec);
return 0;
} }
device_initcall(init_cr16_clocksource);