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[PATCH][AArch64] Stop redundant zero-extension after UMOV when in DI mode 

This patch extends the aarch64_get_lane_zero_extendsi instruction
definition to also cover DI mode. This prevents a redundant AND
instruction from being generated due to the pattern failing to be matched.

Committed on behalf of Sam Tebbs.

gcc/
2018-08-01  Sam Tebbs  <sam.tebbs@arm.com>

	* config/aarch64/aarch64-simd.md
	(*aarch64_get_lane_zero_extendsi<mode>): Rename to...
	(*aarch64_get_lane_zero_extend<GPI:mode><VDQQH:mode>): ... This and
	use GPI iterator instead of SI mode.

gcc/testsuite
2018-08-01  Sam Tebbs  <sam.tebbs@arm.com>

	* gcc.target/aarch64/extract_zero_extend.c: New file.

From-SVN: r263200
This commit is contained in:
Sam Tebbs 2018-08-01 10:10:28 +00:00 committed by Sudakshina Das
parent 5922dcb5cc
commit 00d29b97d9
4 changed files with 108 additions and 15 deletions
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7
gcc/ChangeLog
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@ -1,3 +1,10 @@
2018-08-01 Sam Tebbs <sam.tebbs@arm.com>
* config/aarch64/aarch64-simd.md
(*aarch64_get_lane_zero_extendsi<mode>): Rename to...
(*aarch64_get_lane_zero_extend<GPI:mode><VDQQH:mode>): ... This and
use GPI iterator instead of SI mode.
2018-08-01 Richard Earnshaw <rearnsha@arm.com>
* config/rs6000/rs6000.md (speculation_barrier): Renamed from

31
gcc/config/aarch64/aarch64-simd.md
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@ -3030,21 +3030,22 @@
operands[2] = aarch64_endian_lane_rtx (<MODE>mode, INTVAL (operands[2]));
return "smov\\t%<GPI:w>0, %1.<VDQQH:Vetype>[%2]";
}
[(set_attr "type" "neon_to_gp<q>")]
)
(define_insn "*aarch64_get_lane_zero_extendsi<mode>"
[(set (match_operand:SI 0 "register_operand" "=r")
(zero_extend:SI
(vec_select:<VEL>
(match_operand:VDQQH 1 "register_operand" "w")
(parallel [(match_operand:SI 2 "immediate_operand" "i")]))))]
"TARGET_SIMD"
{
operands[2] = aarch64_endian_lane_rtx (<MODE>mode, INTVAL (operands[2]));
return "umov\\t%w0, %1.<Vetype>[%2]";
}
[(set_attr "type" "neon_to_gp<q>")]
[(set_attr "type" "neon_to_gp<q>")]
)
(define_insn "*aarch64_get_lane_zero_extend<GPI:mode><VDQQH:mode>"
[(set (match_operand:GPI 0 "register_operand" "=r")
(zero_extend:GPI
(vec_select:<VEL>
(match_operand:VDQQH 1 "register_operand" "w")
(parallel [(match_operand:SI 2 "immediate_operand" "i")]))))]
"TARGET_SIMD"
{
operands[2] = aarch64_endian_lane_rtx (<VDQQH:MODE>mode,
INTVAL (operands[2]));
return "umov\\t%w0, %1.<Vetype>[%2]";
}
[(set_attr "type" "neon_to_gp<q>")]
)
;; Lane extraction of a value, neither sign nor zero extension

4
gcc/testsuite/ChangeLog
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@ -1,3 +1,7 @@
2018-08-01 Sam Tebbs <sam.tebbs@arm.com>
* gcc.target/aarch64/extract_zero_extend.c: New file.
2018-08-01 Jakub Jelinek <jakub@redhat.com>
PR c/85704

81
gcc/testsuite/gcc.target/aarch64/extract_zero_extend.c Normal file
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@ -0,0 +1,81 @@
/* { dg-do compile } */
/* { dg-options "-O3 -fdump-rtl-final" } */
/* Tests div16qi. */
typedef unsigned char div16qi __attribute__ ((vector_size (16)));
/* Tests div8qi. */
typedef unsigned char div8qi __attribute__ ((vector_size (8)));
/* Tests div8hi. */
typedef unsigned short div8hi __attribute__ ((vector_size (16)));
/* Tests div4hi. */
typedef unsigned short div4hi __attribute__ ((vector_size (8)));
/* Tests siv16qi. */
typedef unsigned char siv16qi __attribute__ ((vector_size (16)));
/* Tests siv8qi. */
typedef unsigned char siv8qi __attribute__ ((vector_size (8)));
/* Tests siv8hi. */
typedef unsigned short siv8hi __attribute__ ((vector_size (16)));
/* Tests siv4hi. */
typedef unsigned short siv4hi __attribute__ ((vector_size (8)));
unsigned long long
foo_div16qi (div16qi a)
{
return a[0];
}
unsigned long long
foo_div8qi (div8qi a)
{
return a[0];
}
unsigned long long
foo_div8hi (div8hi a)
{
return a[0];
}
unsigned long long
foo_div4hi (div4hi a)
{
return a[0];
}
unsigned int
foo_siv16qi (siv16qi a)
{
return a[0];
}
unsigned int
foo_siv8qi (siv8qi a)
{
return a[0];
}
unsigned int
foo_siv8hi (siv8hi a)
{
return a[0];
}
unsigned int
foo_siv4hi (siv4hi a)
{
return a[0];
}
/* { dg-final { scan-assembler-times "umov\\t" 8 } } */
/* { dg-final { scan-assembler-not "and\\t" } } */
/* { dg-final { scan-rtl-dump "aarch64_get_lane_zero_extenddiv16qi" "final" } } */
/* { dg-final { scan-rtl-dump "aarch64_get_lane_zero_extenddiv8qi" "final" } } */
/* { dg-final { scan-rtl-dump "aarch64_get_lane_zero_extenddiv8hi" "final" } } */
/* { dg-final { scan-rtl-dump "aarch64_get_lane_zero_extenddiv4hi" "final" } } */
/* { dg-final { scan-rtl-dump "aarch64_get_lane_zero_extendsiv16qi" "final" } } */
/* { dg-final { scan-rtl-dump "aarch64_get_lane_zero_extendsiv8qi" "final" } } */
/* { dg-final { scan-rtl-dump "aarch64_get_lane_zero_extendsiv8hi" "final" } } */
/* { dg-final { scan-rtl-dump "aarch64_get_lane_zero_extendsiv4hi" "final" } } */