mirror of git://gcc.gnu.org/git/gcc.git
2012-06-19 Tom de Vries <vries@codesourcery.com>
Maxim Kuvyrkov <maxim@codesourcery.com> * config/mips/mips.c (mips_emit_pre_atomic_barrier_p,) (mips_emit_post_atomic_barrier_p): New static functions. (mips_process_sync_loop): Use them. Emit sync memory barriers in accordance with memory model semantics. Add return of CMP result for compare_and_swap. * config/mips/mips.md: Update comment. (sync_cmp): New attribute. (sync_memmodel): New attribute replacing sync_release_barrier. * config/mips/sync.md (UNSPEC_ATOMIC_COMPARE_AND_SWAP,) (UNSPEC_ATOMIC_EXCHANGE, UNSPEC_ATOMIC_FETCH_OP): New constants. (sync_lock_test_and_set, test_and_set_12): Update. (atomic_compare_and_swap, atomic_exchange, atomic_exchange_llsc,) (atomic_fetch_add, atomic_fetch_add_llsc): New patterns. Co-Authored-By: Maxim Kuvyrkov <maxim@codesourcery.com> From-SVN: r188803
This commit is contained in:
Tom de Vries
Maxim Kuvyrkov
parent
e98f6824d6
commit
01c196ea91
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@ -1,3 +1,20 @@
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2012-06-19 Tom de Vries <vries@codesourcery.com>
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Maxim Kuvyrkov <maxim@codesourcery.com>
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* config/mips/mips.c (mips_emit_pre_atomic_barrier_p,)
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(mips_emit_post_atomic_barrier_p): New static functions.
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(mips_process_sync_loop): Use them. Emit sync memory barriers in
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accordance with memory model semantics. Add return of CMP result for
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compare_and_swap.
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* config/mips/mips.md: Update comment.
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(sync_cmp): New attribute.
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(sync_memmodel): New attribute replacing sync_release_barrier.
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* config/mips/sync.md (UNSPEC_ATOMIC_COMPARE_AND_SWAP,)
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(UNSPEC_ATOMIC_EXCHANGE, UNSPEC_ATOMIC_FETCH_OP): New constants.
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(sync_lock_test_and_set, test_and_set_12): Update.
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(atomic_compare_and_swap, atomic_exchange, atomic_exchange_llsc,)
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(atomic_fetch_add, atomic_fetch_add_llsc): New patterns.
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2012-06-19 Joseph Myers <joseph@codesourcery.com>
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* config/rs6000/spe.md (*mov_si<mode>_e500_subreg0): Rename to
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@ -11976,6 +11976,45 @@ mips_sync_insn2_template (enum attr_sync_insn2 type)
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gcc_unreachable ();
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}
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/* Subroutines of the mips_process_sync_loop.
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Emit barriers as needed for the memory MODEL. */
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static bool
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mips_emit_pre_atomic_barrier_p (enum memmodel model)
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{
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switch (model)
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{
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case MEMMODEL_RELAXED:
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case MEMMODEL_CONSUME:
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case MEMMODEL_ACQUIRE:
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return false;
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case MEMMODEL_RELEASE:
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case MEMMODEL_ACQ_REL:
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case MEMMODEL_SEQ_CST:
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return true;
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default:
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gcc_unreachable ();
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}
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}
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static bool
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mips_emit_post_atomic_barrier_p (enum memmodel model)
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{
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switch (model)
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{
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case MEMMODEL_RELAXED:
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case MEMMODEL_CONSUME:
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case MEMMODEL_RELEASE:
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return false;
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case MEMMODEL_ACQUIRE:
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case MEMMODEL_ACQ_REL:
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case MEMMODEL_SEQ_CST:
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return true;
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default:
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gcc_unreachable ();
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}
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}
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/* OPERANDS are the operands to a sync loop instruction and INDEX is
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the value of the one of the sync_* attributes. Return the operand
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referred to by the attribute, or DEFAULT_VALUE if the insn doesn't
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@ -11996,11 +12035,13 @@ static void
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mips_process_sync_loop (rtx insn, rtx *operands)
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{
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rtx at, mem, oldval, newval, inclusive_mask, exclusive_mask;
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rtx required_oldval, insn1_op2, tmp1, tmp2, tmp3;
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rtx required_oldval, insn1_op2, tmp1, tmp2, tmp3, cmp;
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unsigned int tmp3_insn;
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enum attr_sync_insn1 insn1;
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enum attr_sync_insn2 insn2;
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bool is_64bit_p;
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int memmodel_attr;
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enum memmodel model;
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/* Read an operand from the sync_WHAT attribute and store it in
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variable WHAT. DEFAULT is the default value if no attribute
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@ -12017,6 +12058,7 @@ mips_process_sync_loop (rtx insn, rtx *operands)
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/* Read the other attributes. */
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at = gen_rtx_REG (GET_MODE (mem), AT_REGNUM);
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READ_OPERAND (oldval, at);
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READ_OPERAND (cmp, 0);
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READ_OPERAND (newval, at);
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READ_OPERAND (inclusive_mask, 0);
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READ_OPERAND (exclusive_mask, 0);
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@ -12025,10 +12067,23 @@ mips_process_sync_loop (rtx insn, rtx *operands)
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insn1 = get_attr_sync_insn1 (insn);
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insn2 = get_attr_sync_insn2 (insn);
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memmodel_attr = get_attr_sync_memmodel (insn);
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switch (memmodel_attr)
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{
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case 10:
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model = MEMMODEL_ACQ_REL;
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break;
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case 11:
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model = MEMMODEL_ACQUIRE;
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break;
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default:
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model = INTVAL (operands[memmodel_attr]);
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}
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mips_multi_start ();
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/* Output the release side of the memory barrier. */
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if (get_attr_sync_release_barrier (insn) == SYNC_RELEASE_BARRIER_YES)
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if (mips_emit_pre_atomic_barrier_p (model))
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{
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if (required_oldval == 0 && TARGET_OCTEON)
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{
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@ -12066,6 +12121,10 @@ mips_process_sync_loop (rtx insn, rtx *operands)
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tmp1 = at;
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}
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mips_multi_add_insn ("bne\t%0,%z1,2f", tmp1, required_oldval, NULL);
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/* CMP = 0 [delay slot]. */
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if (cmp)
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mips_multi_add_insn ("li\t%0,0", cmp, NULL);
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}
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/* $TMP1 = OLDVAL & EXCLUSIVE_MASK. */
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@ -12129,11 +12188,15 @@ mips_process_sync_loop (rtx insn, rtx *operands)
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mips_multi_copy_insn (tmp3_insn);
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mips_multi_set_operand (mips_multi_last_index (), 0, newval);
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}
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else
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else if (!(required_oldval && cmp))
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mips_multi_add_insn ("nop", NULL);
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/* CMP = 1 -- either standalone or in a delay slot. */
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if (required_oldval && cmp)
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mips_multi_add_insn ("li\t%0,1", cmp, NULL);
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/* Output the acquire side of the memory barrier. */
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if (TARGET_SYNC_AFTER_SC)
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if (TARGET_SYNC_AFTER_SC && mips_emit_post_atomic_barrier_p (model))
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mips_multi_add_insn ("sync", NULL);
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/* Output the exit label, if needed. */
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@ -349,13 +349,15 @@
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;; if (RELEASE_BARRIER == YES) sync
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;; 1: OLDVAL = *MEM
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;; if ((OLDVAL & INCLUSIVE_MASK) != REQUIRED_OLDVAL) goto 2
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;; CMP = 0 [delay slot]
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;; $TMP1 = OLDVAL & EXCLUSIVE_MASK
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;; $TMP2 = INSN1 (OLDVAL, INSN1_OP2)
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;; $TMP3 = INSN2 ($TMP2, INCLUSIVE_MASK)
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;; $AT |= $TMP1 | $TMP3
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;; if (!commit (*MEM = $AT)) goto 1.
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;; if (INSN1 != MOVE && INSN1 != LI) NEWVAL = $TMP3 [delay slot]
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;; sync
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;; CMP = 1
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;; if (ACQUIRE_BARRIER == YES) sync
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;; 2:
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;;
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;; where "$" values are temporaries and where the other values are
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@ -364,6 +366,7 @@
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;; specified, the following values are used instead:
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;;
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;; - OLDVAL: $AT
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;; - CMP: NONE
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;; - NEWVAL: $AT
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;; - INCLUSIVE_MASK: -1
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;; - REQUIRED_OLDVAL: OLDVAL & INCLUSIVE_MASK
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@ -375,6 +378,7 @@
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;; but the gen* programs don't yet support that.
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(define_attr "sync_mem" "none,0,1,2,3,4,5" (const_string "none"))
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(define_attr "sync_oldval" "none,0,1,2,3,4,5" (const_string "none"))
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(define_attr "sync_cmp" "none,0,1,2,3,4,5" (const_string "none"))
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(define_attr "sync_newval" "none,0,1,2,3,4,5" (const_string "none"))
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(define_attr "sync_inclusive_mask" "none,0,1,2,3,4,5" (const_string "none"))
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(define_attr "sync_exclusive_mask" "none,0,1,2,3,4,5" (const_string "none"))
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@ -384,8 +388,11 @@
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(const_string "move"))
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(define_attr "sync_insn2" "nop,and,xor,not"
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(const_string "nop"))
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(define_attr "sync_release_barrier" "yes,no"
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(const_string "yes"))
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;; Memory model specifier.
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;; "0"-"9" values specify the operand that stores the memory model value.
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;; "10" specifies MEMMODEL_ACQ_REL,
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;; "11" specifies MEMMODEL_ACQUIRE.
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(define_attr "sync_memmodel" "" (const_int 10))
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;; Length of instruction in bytes.
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(define_attr "length" ""
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@ -29,6 +29,9 @@
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UNSPEC_SYNC_EXCHANGE
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UNSPEC_SYNC_EXCHANGE_12
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UNSPEC_MEMORY_BARRIER
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UNSPEC_ATOMIC_COMPARE_AND_SWAP
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UNSPEC_ATOMIC_EXCHANGE
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UNSPEC_ATOMIC_FETCH_OP
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])
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;; Atomic fetch bitwise operations.
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@ -54,6 +57,7 @@
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"GENERATE_SYNC"
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{ return mips_output_sync (); })
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;; Can be removed in favor of atomic_compare_and_swap below.
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(define_insn "sync_compare_and_swap<mode>"
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[(set (match_operand:GPR 0 "register_operand" "=&d,&d")
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(match_operand:GPR 1 "memory_operand" "+R,R"))
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@ -368,6 +372,7 @@
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(set_attr "sync_mem" "0")
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(set_attr "sync_insn1_op2" "1")])
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;; Can be removed in favor of atomic_fetch_add below.
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(define_insn "sync_old_add<mode>"
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[(set (match_operand:GPR 0 "register_operand" "=&d,&d")
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(match_operand:GPR 1 "memory_operand" "+R,R"))
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@ -521,7 +526,7 @@
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UNSPEC_SYNC_EXCHANGE))]
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"GENERATE_LL_SC"
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{ return mips_output_sync_loop (insn, operands); }
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[(set_attr "sync_release_barrier" "no")
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[(set_attr "sync_memmodel" "11")
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(set_attr "sync_insn1" "li,move")
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(set_attr "sync_oldval" "0")
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(set_attr "sync_mem" "1")
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@ -550,7 +555,7 @@
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UNSPEC_SYNC_EXCHANGE_12))]
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"GENERATE_LL_SC"
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{ return mips_output_sync_loop (insn, operands); }
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[(set_attr "sync_release_barrier" "no")
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[(set_attr "sync_memmodel" "11")
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(set_attr "sync_oldval" "0")
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(set_attr "sync_mem" "1")
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;; Unused, but needed to give the number of operands expected by
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@ -558,3 +563,101 @@
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(set_attr "sync_inclusive_mask" "2")
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(set_attr "sync_exclusive_mask" "3")
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(set_attr "sync_insn1_op2" "4")])
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(define_insn "atomic_compare_and_swap<mode>"
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[(set (match_operand:GPR 0 "register_operand" "=&d,&d")
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;; Logically this unspec is an "eq" operator, but we need to obscure
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;; reads and writes from/to memory with an unspec to prevent
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;; optimizations on shared memory locations. Otherwise, comparison in
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;; { mem = 2; if (atomic_cmp_swap(mem,...) == 2) ...; }
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;; would be optimized away. In addition to that we need to use
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;; unspec_volatile, not just plain unspec -- for the sake of other
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;; threads -- to make sure we don't remove the entirety of the pattern
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;; just because current thread doesn't observe any effect from it.
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;; TODO: the obscuring unspec can be relaxed for permissive memory
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;; models.
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;; Same applies to other atomic_* patterns.
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(unspec_volatile:GPR [(match_operand:GPR 2 "memory_operand" "+R,R")
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(match_operand:GPR 3 "reg_or_0_operand" "dJ,dJ")]
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UNSPEC_ATOMIC_COMPARE_AND_SWAP))
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(set (match_operand:GPR 1 "register_operand" "=&d,&d")
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(unspec_volatile:GPR [(match_dup 2)]
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UNSPEC_ATOMIC_COMPARE_AND_SWAP))
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(set (match_dup 2)
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(unspec_volatile:GPR [(match_dup 2)
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(match_dup 3)
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(match_operand:GPR 4 "arith_operand" "I,d")]
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UNSPEC_ATOMIC_COMPARE_AND_SWAP))
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(unspec_volatile:GPR [(match_operand:SI 5 "const_int_operand")
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(match_operand:SI 6 "const_int_operand")
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(match_operand:SI 7 "const_int_operand")]
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UNSPEC_ATOMIC_COMPARE_AND_SWAP)]
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"GENERATE_LL_SC"
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{ return mips_output_sync_loop (insn, operands); }
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[(set_attr "sync_insn1" "li,move")
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(set_attr "sync_oldval" "1")
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(set_attr "sync_cmp" "0")
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(set_attr "sync_mem" "2")
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(set_attr "sync_required_oldval" "3")
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(set_attr "sync_insn1_op2" "4")
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(set_attr "sync_memmodel" "6")])
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(define_expand "atomic_exchange<mode>"
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[(match_operand:GPR 0 "register_operand")
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(match_operand:GPR 1 "memory_operand")
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(match_operand:GPR 2 "arith_operand")
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(match_operand:SI 3 "const_int_operand")]
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"GENERATE_LL_SC"
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{
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emit_insn (gen_atomic_exchange<mode>_llsc (operands[0], operands[1],
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operands[2], operands[3]));
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DONE;
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})
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(define_insn "atomic_exchange<mode>_llsc"
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[(set (match_operand:GPR 0 "register_operand" "=&d,&d")
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(unspec_volatile:GPR [(match_operand:GPR 1 "memory_operand" "+R,R")]
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UNSPEC_ATOMIC_EXCHANGE))
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(set (match_dup 1)
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(unspec_volatile:GPR [(match_operand:GPR 2 "arith_operand" "I,d")]
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UNSPEC_ATOMIC_EXCHANGE))
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(unspec_volatile:GPR [(match_operand:SI 3 "const_int_operand")]
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UNSPEC_ATOMIC_EXCHANGE)]
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"GENERATE_LL_SC"
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{ return mips_output_sync_loop (insn, operands); }
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[(set_attr "sync_insn1" "li,move")
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(set_attr "sync_oldval" "0")
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(set_attr "sync_mem" "1")
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(set_attr "sync_insn1_op2" "2")
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(set_attr "sync_memmodel" "3")])
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(define_expand "atomic_fetch_add<mode>"
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[(match_operand:GPR 0 "register_operand")
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(match_operand:GPR 1 "memory_operand")
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(match_operand:GPR 2 "arith_operand")
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(match_operand:SI 3 "const_int_operand")]
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"GENERATE_LL_SC"
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{
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emit_insn (gen_atomic_fetch_add<mode>_llsc (operands[0], operands[1],
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operands[2], operands[3]));
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DONE;
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})
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(define_insn "atomic_fetch_add<mode>_llsc"
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[(set (match_operand:GPR 0 "register_operand" "=&d,&d")
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(unspec_volatile:GPR [(match_operand:GPR 1 "memory_operand" "+R,R")]
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UNSPEC_ATOMIC_FETCH_OP))
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(set (match_dup 1)
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(unspec_volatile:GPR
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[(plus:GPR (match_dup 1)
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(match_operand:GPR 2 "arith_operand" "I,d"))]
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UNSPEC_ATOMIC_FETCH_OP))
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(unspec_volatile:GPR [(match_operand:SI 3 "const_int_operand")]
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UNSPEC_ATOMIC_FETCH_OP)]
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"GENERATE_LL_SC"
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{ return mips_output_sync_loop (insn, operands); }
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[(set_attr "sync_insn1" "addiu,addu")
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(set_attr "sync_oldval" "0")
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(set_attr "sync_mem" "1")
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(set_attr "sync_insn1_op2" "2")
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(set_attr "sync_memmodel" "3")])
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