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Backport: [GCC, ARM] armv8 linux toolchain asan testcase fail due to stl missing conditional code 

Backport from mainline
	2015-06-09  Shiva Chen  <shiva0217@gmail.com>

	* sync.md (atomic_load<mode>): Add conditional code for lda/ldr
	(atomic_store<mode>): Likewise.

	* gcc.target/arm/stl-cond.c: New test.

From-SVN: r228322
This commit is contained in:
Kyrylo Tkachov 2015-10-01 09:05:45 +00:00 committed by Kyrylo Tkachov
parent 718ea49c77
commit 06f2270637
4 changed files with 42 additions and 6 deletions
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8
gcc/ChangeLog
View File

@ -1,3 +1,11 @@
2015-10-01 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Backport from mainline
2015-06-09 Shiva Chen <shiva0217@gmail.com>
* sync.md (atomic_load<mode>): Add conditional code for lda/ldr
(atomic_store<mode>): Likewise.
2015-09-30 H.J. Lu <hongjiu.lu@intel.com> 2015-09-30 H.J. Lu <hongjiu.lu@intel.com>
Backport from mainline Backport from mainline

14
gcc/config/arm/sync.md
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@ -75,11 +75,12 @@
{ {
enum memmodel model = memmodel_from_int (INTVAL (operands[2])); enum memmodel model = memmodel_from_int (INTVAL (operands[2]));
if (is_mm_relaxed (model) || is_mm_consume (model) || is_mm_release (model)) if (is_mm_relaxed (model) || is_mm_consume (model) || is_mm_release (model))
return \"ldr<sync_sfx>\\t%0, %1\"; return \"ldr%(<sync_sfx>%)\\t%0, %1\";
else else
return \"lda<sync_sfx>\\t%0, %1\"; return \"lda<sync_sfx>%?\\t%0, %1\";
} }
) [(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(define_insn "atomic_store<mode>" (define_insn "atomic_store<mode>"
[(set (match_operand:QHSI 0 "memory_operand" "=Q") [(set (match_operand:QHSI 0 "memory_operand" "=Q")
@ -91,11 +92,12 @@
{ {
enum memmodel model = memmodel_from_int (INTVAL (operands[2])); enum memmodel model = memmodel_from_int (INTVAL (operands[2]));
if (is_mm_relaxed (model) || is_mm_consume (model) || is_mm_acquire (model)) if (is_mm_relaxed (model) || is_mm_consume (model) || is_mm_acquire (model))
return \"str<sync_sfx>\t%1, %0\"; return \"str%(<sync_sfx>%)\t%1, %0\";
else else
return \"stl<sync_sfx>\t%1, %0\"; return \"stl<sync_sfx>%?\t%1, %0\";
} }
) [(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
;; Note that ldrd and vldr are *not* guaranteed to be single-copy atomic, ;; Note that ldrd and vldr are *not* guaranteed to be single-copy atomic,
;; even for a 64-bit aligned address. Instead we use a ldrexd unparied ;; even for a 64-bit aligned address. Instead we use a ldrexd unparied

7
gcc/testsuite/ChangeLog
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@ -1,3 +1,10 @@
2015-10-01 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Backport from mainline
2015-06-09 Shiva Chen <shiva0217@gmail.com>
* gcc.target/arm/stl-cond.c: New test.
2015-09-30 H.J. Lu <hongjiu.lu@intel.com> 2015-09-30 H.J. Lu <hongjiu.lu@intel.com>
Backport from mainline Backport from mainline

19
gcc/testsuite/gcc.target/arm/stl-cond.c Normal file
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@ -0,0 +1,19 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_arm_ok } */
/* { dg-require-effective-target arm_arch_v8a_ok } */
/* { dg-options "-O2 -marm" } */
/* { dg-add-options arm_arch_v8a } */
struct backtrace_state
{
int threaded;
int lock_alloc;
};
void foo (struct backtrace_state *state)
{
if (state->threaded)
__sync_lock_release (&state->lock_alloc);
}
/* { dg-final { scan-assembler "stlne" } } */