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re PR target/32433 (Code for __builtin_ffs does not benefit from compiler optimizations) 

PR target/32433
        * config/i386/i386.md (ffssi2): Expand as ffs_cmove for TARGET_CMOVE.
        (ffs_cmove): New expander to expand using ctz pattern.
        (*ffs_cmove): Remove pattern.
        (*ffs_no_cmove): Enable only for !TARGET_CMOVE.
        (ffsdi2): Expand using ctz pattern.
        (*ffs_rex64): Remove pattern.

From-SVN: r126154
This commit is contained in:
Uros Bizjak 2007-06-30 19:05:49 +02:00 committed by Uros Bizjak
parent eb2c598d55
commit 08024fb584
2 changed files with 35 additions and 34 deletions
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10
gcc/ChangeLog
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@ -1,3 +1,13 @@
2007-06-30 Uros Bizjak <ubizjak@gmail.com>
PR target/32433
* config/i386/i386.md (ffssi2): Expand as ffs_cmove for TARGET_CMOVE.
(ffs_cmove): New expander to expand using ctz pattern.
(*ffs_cmove): Remove pattern.
(*ffs_no_cmove): Enable only for !TARGET_CMOVE.
(ffsdi2): Expand using ctz pattern.
(*ffs_rex64): Remove pattern.
2007-06-30 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 2007-06-30 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
PR rtl-optimization/32296 PR rtl-optimization/32296

59
gcc/config/i386/i386.md
View File

@ -14586,36 +14586,40 @@
(clobber (match_scratch:SI 2 "")) (clobber (match_scratch:SI 2 ""))
(clobber (reg:CC FLAGS_REG))])] (clobber (reg:CC FLAGS_REG))])]
"" ""
"") {
if (TARGET_CMOVE)
{
emit_insn (gen_ffs_cmove (operands[0], operands[1]));
DONE;
}
})
(define_insn_and_split "*ffs_cmove" (define_expand "ffs_cmove"
[(set (match_operand:SI 0 "register_operand" "=r")
(ffs:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))
(clobber (match_scratch:SI 2 "=&r"))
(clobber (reg:CC FLAGS_REG))]
"TARGET_CMOVE"
"#"
"&& reload_completed"
[(set (match_dup 2) (const_int -1)) [(set (match_dup 2) (const_int -1))
(parallel [(set (reg:CCZ FLAGS_REG) (compare:CCZ (match_dup 1) (const_int 0))) (parallel [(set (reg:CCZ FLAGS_REG)
(set (match_dup 0) (ctz:SI (match_dup 1)))]) (compare:CCZ (match_operand:SI 1 "register_operand" "")
(const_int 0)))
(set (match_operand:SI 0 "nonimmediate_operand" "")
(ctz:SI (match_dup 1)))])
(set (match_dup 0) (if_then_else:SI (set (match_dup 0) (if_then_else:SI
(eq (reg:CCZ FLAGS_REG) (const_int 0)) (eq (reg:CCZ FLAGS_REG) (const_int 0))
(match_dup 2) (match_dup 2)
(match_dup 0))) (match_dup 0)))
(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1))) (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))
(clobber (reg:CC FLAGS_REG))])] (clobber (reg:CC FLAGS_REG))])]
"") "TARGET_CMOVE"
"operands[2] = gen_reg_rtx (SImode);")
(define_insn_and_split "*ffs_no_cmove" (define_insn_and_split "*ffs_no_cmove"
[(set (match_operand:SI 0 "nonimmediate_operand" "=r") [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
(ffs:SI (match_operand:SI 1 "nonimmediate_operand" "rm"))) (ffs:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))
(clobber (match_scratch:SI 2 "=&q")) (clobber (match_scratch:SI 2 "=&q"))
(clobber (reg:CC FLAGS_REG))] (clobber (reg:CC FLAGS_REG))]
"" "!TARGET_CMOVE"
"#" "#"
"reload_completed" "&& reload_completed"
[(parallel [(set (reg:CCZ FLAGS_REG) (compare:CCZ (match_dup 1) (const_int 0))) [(parallel [(set (reg:CCZ FLAGS_REG)
(compare:CCZ (match_dup 1) (const_int 0)))
(set (match_dup 0) (ctz:SI (match_dup 1)))]) (set (match_dup 0) (ctz:SI (match_dup 1)))])
(set (strict_low_part (match_dup 3)) (set (strict_low_part (match_dup 3))
(eq:QI (reg:CCZ FLAGS_REG) (const_int 0))) (eq:QI (reg:CCZ FLAGS_REG) (const_int 0)))
@ -14641,33 +14645,20 @@
[(set_attr "prefix_0f" "1")]) [(set_attr "prefix_0f" "1")])
(define_expand "ffsdi2" (define_expand "ffsdi2"
[(parallel
[(set (match_operand:DI 0 "register_operand" "")
(ffs:DI (match_operand:DI 1 "nonimmediate_operand" "")))
(clobber (match_scratch:DI 2 ""))
(clobber (reg:CC FLAGS_REG))])]
"TARGET_64BIT && TARGET_CMOVE"
"")
(define_insn_and_split "*ffs_rex64"
[(set (match_operand:DI 0 "register_operand" "=r")
(ffs:DI (match_operand:DI 1 "nonimmediate_operand" "rm")))
(clobber (match_scratch:DI 2 "=&r"))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && TARGET_CMOVE"
"#"
"&& reload_completed"
[(set (match_dup 2) (const_int -1)) [(set (match_dup 2) (const_int -1))
(parallel [(set (reg:CCZ FLAGS_REG) (parallel [(set (reg:CCZ FLAGS_REG)
(compare:CCZ (match_dup 1) (const_int 0))) (compare:CCZ (match_operand:DI 1 "register_operand" "")
(set (match_dup 0) (ctz:DI (match_dup 1)))]) (const_int 0)))
(set (match_operand:DI 0 "nonimmediate_operand" "")
(ctz:DI (match_dup 1)))])
(set (match_dup 0) (if_then_else:DI (set (match_dup 0) (if_then_else:DI
(eq (reg:CCZ FLAGS_REG) (const_int 0)) (eq (reg:CCZ FLAGS_REG) (const_int 0))
(match_dup 2) (match_dup 2)
(match_dup 0))) (match_dup 0)))
(parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 1))) (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 1)))
(clobber (reg:CC FLAGS_REG))])] (clobber (reg:CC FLAGS_REG))])]
"") "TARGET_64BIT"
"operands[2] = gen_reg_rtx (DImode);")
(define_insn "*ffsdi_1" (define_insn "*ffsdi_1"
[(set (reg:CCZ FLAGS_REG) [(set (reg:CCZ FLAGS_REG)