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Remove separate movtf pattern - Use an iterator for all FP modes. 

movtf is unnecessary as a separate expander. Move this to be with
the standard scalar floating point expanders.

Achieved by adding a new iterator and then using the same.

Tested cross aarch64-none-elf and no regressions.

Rebased version from https://gcc.gnu.org/ml/gcc-patches/2015-09/msg00767.html


2015-09-10  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>

	PR target/63304
        * config/aarch64/aarch.md (mov<mode>:GPF_F16): Use GPF_TF_F16.
        (movtf): Delete.
        * config/aarch64/iterators.md (GPF_TF_F16): New.
        (GPF_F16): Delete.

From-SVN: r227679
This commit is contained in:
Ramana Radhakrishnan 2015-09-11 09:44:26 +00:00 committed by Ramana Radhakrishnan
parent 708d1034db
commit 09fcd8e149
3 changed files with 12 additions and 22 deletions
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8
gcc/ChangeLog
View File

@ -1,3 +1,11 @@
2015-09-10 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
PR target/63304
* config/aarch64/aarch.md (mov<mode>:GPF_F16): Use GPF_TF_F16.
(movtf): Delete.
* config/aarch64/iterators.md (GPF_TF_F16): New.
(GPF_F16): Delete.
2015-09-10 Nathan Sidwell <nathan@acm.org> 2015-09-10 Nathan Sidwell <nathan@acm.org>
* config/nvptx/nvptx.c (nvptx_expand_call): Add spacing. * config/nvptx/nvptx.c (nvptx_expand_call): Add spacing.

22
gcc/config/aarch64/aarch64.md
View File

@ -1099,8 +1099,8 @@
}) })
(define_expand "mov<mode>" (define_expand "mov<mode>"
[(set (match_operand:GPF_F16 0 "nonimmediate_operand" "") [(set (match_operand:GPF_TF_F16 0 "nonimmediate_operand" "")
(match_operand:GPF_F16 1 "general_operand" ""))] (match_operand:GPF_TF_F16 1 "general_operand" ""))]
"" ""
{ {
if (!TARGET_FLOAT) if (!TARGET_FLOAT)
@ -1174,24 +1174,6 @@
f_loadd,f_stored,load1,store1,mov_reg")] f_loadd,f_stored,load1,store1,mov_reg")]
) )
(define_expand "movtf"
[(set (match_operand:TF 0 "nonimmediate_operand" "")
(match_operand:TF 1 "general_operand" ""))]
""
{
if (!TARGET_FLOAT)
{
aarch64_err_no_fpadvsimd (TFmode, "code");
FAIL;
}
if (GET_CODE (operands[0]) == MEM
&& ! (GET_CODE (operands[1]) == CONST_DOUBLE
&& aarch64_float_const_zero_rtx_p (operands[1])))
operands[1] = force_reg (TFmode, operands[1]);
}
)
(define_insn "*movtf_aarch64" (define_insn "*movtf_aarch64"
[(set (match_operand:TF 0 [(set (match_operand:TF 0
"nonimmediate_operand" "=w,?&r,w ,?r,w,?w,w,m,?r ,Ump,Ump") "nonimmediate_operand" "=w,?&r,w ,?r,w,?w,w,m,?r ,Ump,Ump")

4
gcc/config/aarch64/iterators.md
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@ -38,8 +38,8 @@
;; Iterator for General Purpose Floating-point registers (32- and 64-bit modes) ;; Iterator for General Purpose Floating-point registers (32- and 64-bit modes)
(define_mode_iterator GPF [SF DF]) (define_mode_iterator GPF [SF DF])
;; Iterator for General Purpose Float registers, inc __fp16. ;; Iterator for all scalar floating point modes (HF, SF, DF and TF)
(define_mode_iterator GPF_F16 [HF SF DF]) (define_mode_iterator GPF_TF_F16 [HF SF DF TF])
;; Double vector modes. ;; Double vector modes.
(define_mode_iterator VDF [V2SF V4HF]) (define_mode_iterator VDF [V2SF V4HF])