mirror of git://gcc.gnu.org/git/gcc.git
Add support for SmartMIPS ASE.
2007-07-05 Sandra Loosemore <sandra@codesourcery.com> David Ung <davidu@mips.com> Add support for SmartMIPS ASE. gcc/ * optabs.c (expand_binop_directly): New, broken out from... (expand_binop): Here. Make it try rotating in the other direction even when the second operand isn't constant. * config/mips/mips.md (*lwxs): New. * config/mips/mips.opt (msmartmips): New. * config/mips/mips.c (mips_lwxs_address_p): New. (mips_rtx_costs): Make it recognize scaled indexed addressing. * config/mips/mips.h (TARGET_CPU_CPP_BUILTINS): Define __mips_smartmips when compiling for TARGET_SMARTMIPS. (ISA_HAS_ROR): Define for TARGET_SMARTMIPS. (ISA_HAS_LWXS): New. (ASM_SPEC): Add -msmartmips/-mno-smartmips. * doc/invoke.texi (MIPS Options): Document -msmartmips/-mno-smartmips. * testsuite/gcc.target/mips/smartmips-lwxs.c: New test case. * testsuite/gcc.target/mips/smartmips-ror-1.c: New test case. * testsuite/gcc.target/mips/smartmips-ror-2.c: New test case. * testsuite/gcc.target/mips/smartmips-ror-3.c: New test case. * testsuite/gcc.target/mips/smartmips-ror-4.c: New test case. Co-Authored-By: David Ung <davidu@mips.com> From-SVN: r126370
This commit is contained in:
Sandra Loosemore
Sandra Loosemore
parent
6fd2892a68
commit
0aa222d17b
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@ -1,3 +1,27 @@
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2007-07-05 Sandra Loosemore <sandra@codesourcery.com>
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David Ung <davidu@mips.com>
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Add support for SmartMIPS ASE.
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* optabs.c (expand_binop_directly): New, broken out from...
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(expand_binop): Here. Make it try rotating in the other
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direction even when the second operand isn't constant.
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* config/mips/mips.md (*lwxs): New.
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* config/mips/mips.opt (msmartmips): New.
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* config/mips/mips.c (mips_lwxs_address_p): New.
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(mips_rtx_costs): Make it recognize scaled indexed addressing.
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* config/mips/mips.h (TARGET_CPU_CPP_BUILTINS): Define
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__mips_smartmips when compiling for TARGET_SMARTMIPS.
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(ISA_HAS_ROR): Define for TARGET_SMARTMIPS.
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(ISA_HAS_LWXS): New.
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(ASM_SPEC): Add -msmartmips/-mno-smartmips.
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* doc/invoke.texi (MIPS Options): Document -msmartmips/-mno-smartmips.
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* testsuite/gcc.target/mips/smartmips-lwxs.c: New test case.
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* testsuite/gcc.target/mips/smartmips-ror-1.c: New test case.
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* testsuite/gcc.target/mips/smartmips-ror-2.c: New test case.
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* testsuite/gcc.target/mips/smartmips-ror-3.c: New test case.
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* testsuite/gcc.target/mips/smartmips-ror-4.c: New test case.
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2007-07-05 Dorit Nuzman <dorit@il.ibm.com>
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* tree-vectorizer.c (new_loop_vec_info): Initialize
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@ -2682,6 +2682,26 @@ m16_nsimm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
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return m16_check_op (op, (- 0x7f) << 3, 0x80 << 3, 7);
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}
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/* Return true if ADDR matches the pattern for the lwxs load scaled indexed
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address instruction. */
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static bool
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mips_lwxs_address_p (rtx addr)
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{
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if (ISA_HAS_LWXS
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&& GET_CODE (addr) == PLUS
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&& REG_P (XEXP (addr, 1)))
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{
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rtx offset = XEXP (addr, 0);
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if (GET_CODE (offset) == MULT
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&& REG_P (XEXP (offset, 0))
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&& GET_CODE (XEXP (offset, 1)) == CONST_INT
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&& INTVAL (XEXP (offset, 1)) == 4)
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return true;
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}
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return false;
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}
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static bool
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mips_rtx_costs (rtx x, int code, int outer_code, int *total)
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{
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@ -2778,13 +2798,21 @@ mips_rtx_costs (rtx x, int code, int outer_code, int *total)
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case MEM:
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{
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/* If the address is legitimate, return the number of
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instructions it needs, otherwise use the default handling. */
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int n = mips_address_insns (XEXP (x, 0), GET_MODE (x));
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instructions it needs. */
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rtx addr = XEXP (x, 0);
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int n = mips_address_insns (addr, GET_MODE (x));
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if (n > 0)
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{
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*total = COSTS_N_INSNS (n + 1);
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return true;
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}
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/* Check for scaled indexed address. */
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if (mips_lwxs_address_p (addr))
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{
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*total = COSTS_N_INSNS (2);
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return true;
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}
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/* Otherwise use the default handling. */
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return false;
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}
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@ -367,6 +367,9 @@ extern const struct mips_rtx_cost_data *mips_cost;
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if (TARGET_MIPS3D) \
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builtin_define ("__mips3d"); \
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\
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if (TARGET_SMARTMIPS) \
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builtin_define ("__mips_smartmips"); \
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\
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if (TARGET_DSP) \
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builtin_define ("__mips_dsp"); \
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\
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@ -733,7 +736,8 @@ extern const struct mips_rtx_cost_data *mips_cost;
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#define ISA_HAS_ROR ((ISA_MIPS32R2 \
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|| TARGET_MIPS5400 \
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|| TARGET_MIPS5500 \
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|| TARGET_SR71K) \
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|| TARGET_SR71K \
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|| TARGET_SMARTMIPS) \
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&& !TARGET_MIPS16)
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/* ISA has data prefetch instructions. This controls use of 'pref'. */
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@ -768,6 +772,9 @@ extern const struct mips_rtx_cost_data *mips_cost;
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/* ISA has instructions for accessing top part of 64-bit fp regs. */
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#define ISA_HAS_MXHC1 (TARGET_FLOAT64 && ISA_MIPS32R2)
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/* ISA has lwxs instruction (load w/scaled index address. */
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#define ISA_HAS_LWXS (TARGET_SMARTMIPS && !TARGET_MIPS16)
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/* True if the result of a load is not available to the next instruction.
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A nop will then be needed between instructions like "lw $4,..."
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and "addiu $4,$4,1". */
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@ -883,6 +890,7 @@ extern const struct mips_rtx_cost_data *mips_cost;
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%{mdmx} %{mno-mdmx:-no-mdmx} \
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%{mdsp} %{mno-dsp} \
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%{mdspr2} %{mno-dspr2} \
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%{msmartmips} %{mno-smartmips} \
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%{mmt} %{mno-mt} \
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%{mfix-vr4120} %{mfix-vr4130} \
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%(subtarget_asm_optimizing_spec) \
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@ -3654,6 +3654,21 @@
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[(set_attr "type" "fpidxstore")
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(set_attr "mode" "<ANYF:UNITMODE>")])
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;; Scaled indexed address load.
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;; Per md.texi, we only need to look for a pattern with multiply in the
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;; address expression, not shift.
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(define_insn "*lwxs"
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[(set (match_operand:SI 0 "register_operand" "=d")
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(mem:SI (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
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(const_int 4))
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(match_operand:SI 2 "register_operand" "d"))))]
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"ISA_HAS_LWXS"
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"lwxs\t%0,%1(%2)"
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[(set_attr "type" "load")
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(set_attr "mode" "SI")
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(set_attr "length" "4")])
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;; 16-bit Integer moves
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;; Unlike most other insns, the move insns can't be split with
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@ -209,6 +209,10 @@ msingle-float
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Target Report RejectNegative Mask(SINGLE_FLOAT)
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Restrict the use of hardware floating-point instructions to 32-bit operations
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msmartmips
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Target Report RejectNegative Mask(SMARTMIPS)
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Use SmartMIPS instructions
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msoft-float
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Target Report RejectNegative Mask(SOFT_FLOAT)
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Prevent the use of all hardware floating-point instructions
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@ -622,6 +622,7 @@ Objective-C and Objective-C++ Dialects}.
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-mshared -mno-shared -mxgot -mno-xgot -mgp32 -mgp64 @gol
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-mfp32 -mfp64 -mhard-float -msoft-float @gol
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-msingle-float -mdouble-float -mdsp -mno-dsp -mdspr2 -mno-dspr2 @gol
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-msmartmips -mno-smartmips @gol
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-mpaired-single -mno-paired-single -mdmx -mno-mdmx @gol
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-mips3d -mno-mips3d -mmt -mno-mt @gol
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-mlong64 -mlong32 -msym32 -mno-sym32 @gol
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@ -11662,6 +11663,12 @@ Use (do not use) the MIPS DSP ASE. @xref{MIPS DSP Built-in Functions}.
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Use (do not use) the MIPS DSP ASE REV 2. @xref{MIPS DSP Built-in Functions}.
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The option @option{-mdspr2} implies @option{-mdsp}.
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@item -msmartmips
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@itemx -mno-smartmips
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@opindex msmartmips
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@opindex mno-smartmips
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Use (do not use) the MIPS SmartMIPS ASE.
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@item -mpaired-single
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@itemx -mno-paired-single
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@opindex mpaired-single
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234
gcc/optabs.c
234
gcc/optabs.c
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@ -1246,95 +1246,14 @@ swap_commutative_operands_with_target (rtx target, rtx op0, rtx op1)
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}
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/* Generate code to perform an operation specified by BINOPTAB
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on operands OP0 and OP1, with result having machine-mode MODE.
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UNSIGNEDP is for the case where we have to widen the operands
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to perform the operation. It says to use zero-extension.
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If TARGET is nonzero, the value
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is generated there, if it is convenient to do so.
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In all cases an rtx is returned for the locus of the value;
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this may or may not be TARGET. */
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rtx
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expand_binop (enum machine_mode mode, optab binoptab, rtx op0, rtx op1,
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rtx target, int unsignedp, enum optab_methods methods)
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{
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enum optab_methods next_methods
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= (methods == OPTAB_LIB || methods == OPTAB_LIB_WIDEN
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? OPTAB_WIDEN : methods);
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enum mode_class class;
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enum machine_mode wider_mode;
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rtx temp;
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int commutative_op = 0;
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int shift_op = (binoptab->code == ASHIFT
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|| binoptab->code == ASHIFTRT
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|| binoptab->code == LSHIFTRT
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|| binoptab->code == ROTATE
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|| binoptab->code == ROTATERT);
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rtx entry_last = get_last_insn ();
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rtx last;
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bool first_pass_p = true;
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class = GET_MODE_CLASS (mode);
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/* If subtracting an integer constant, convert this into an addition of
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the negated constant. */
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if (binoptab == sub_optab && GET_CODE (op1) == CONST_INT)
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{
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op1 = negate_rtx (mode, op1);
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binoptab = add_optab;
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}
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/* If we are inside an appropriately-short loop and we are optimizing,
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force expensive constants into a register. */
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if (CONSTANT_P (op0) && optimize
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&& rtx_cost (op0, binoptab->code) > COSTS_N_INSNS (1))
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{
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if (GET_MODE (op0) != VOIDmode)
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op0 = convert_modes (mode, VOIDmode, op0, unsignedp);
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op0 = force_reg (mode, op0);
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}
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if (CONSTANT_P (op1) && optimize
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&& ! shift_op && rtx_cost (op1, binoptab->code) > COSTS_N_INSNS (1))
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{
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if (GET_MODE (op1) != VOIDmode)
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op1 = convert_modes (mode, VOIDmode, op1, unsignedp);
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op1 = force_reg (mode, op1);
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}
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/* Record where to delete back to if we backtrack. */
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last = get_last_insn ();
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/* If operation is commutative,
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try to make the first operand a register.
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Even better, try to make it the same as the target.
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Also try to make the last operand a constant. */
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if (GET_RTX_CLASS (binoptab->code) == RTX_COMM_ARITH
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|| binoptab == smul_widen_optab
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|| binoptab == umul_widen_optab
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|| binoptab == smul_highpart_optab
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|| binoptab == umul_highpart_optab)
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{
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commutative_op = 1;
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if (swap_commutative_operands_with_target (target, op0, op1))
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{
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temp = op1;
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op1 = op0;
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op0 = temp;
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}
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}
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retry:
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/* If we can do it with a three-operand insn, do so. */
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if (methods != OPTAB_MUST_WIDEN
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&& binoptab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
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/* Helper function for expand_binop: handle the case where there
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is an insn that directly implements the indicated operation.
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Returns null if this is not possible. */
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static rtx
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expand_binop_directly (enum machine_mode mode, optab binoptab,
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rtx op0, rtx op1,
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rtx target, int unsignedp, enum optab_methods methods,
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int commutative_op, rtx last)
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{
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int icode = (int) binoptab->handlers[(int) mode].insn_code;
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enum machine_mode mode0 = insn_data[icode].operand[1].mode;
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@ -1342,6 +1261,7 @@ expand_binop (enum machine_mode mode, optab binoptab, rtx op0, rtx op1,
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enum machine_mode tmp_mode;
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rtx pat;
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rtx xop0 = op0, xop1 = op1;
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rtx temp;
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if (target)
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temp = target;
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@ -1416,7 +1336,7 @@ expand_binop (enum machine_mode mode, optab binoptab, rtx op0, rtx op1,
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{
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/* If PAT is composed of more than one insn, try to add an appropriate
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REG_EQUAL note to it. If we can't because TEMP conflicts with an
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operand, call ourselves again, this time without a target. */
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operand, call expand_binop again, this time without a target. */
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if (INSN_P (pat) && NEXT_INSN (pat) != NULL_RTX
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&& ! add_equal_note (pat, temp, binoptab->code, xop0, xop1))
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{
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@ -1428,24 +1348,130 @@ expand_binop (enum machine_mode mode, optab binoptab, rtx op0, rtx op1,
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emit_insn (pat);
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return temp;
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}
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else
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delete_insns_since (last);
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return NULL_RTX;
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}
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/* If we were trying to rotate by a constant value, and that didn't
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work, try rotating the other direction before falling back to
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shifts and bitwise-or. */
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if (first_pass_p
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&& (binoptab == rotl_optab || binoptab == rotr_optab)
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&& class == MODE_INT
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&& GET_CODE (op1) == CONST_INT
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&& INTVAL (op1) > 0
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&& (unsigned int) INTVAL (op1) < GET_MODE_BITSIZE (mode))
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/* Generate code to perform an operation specified by BINOPTAB
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on operands OP0 and OP1, with result having machine-mode MODE.
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UNSIGNEDP is for the case where we have to widen the operands
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to perform the operation. It says to use zero-extension.
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If TARGET is nonzero, the value
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is generated there, if it is convenient to do so.
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In all cases an rtx is returned for the locus of the value;
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this may or may not be TARGET. */
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rtx
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expand_binop (enum machine_mode mode, optab binoptab, rtx op0, rtx op1,
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rtx target, int unsignedp, enum optab_methods methods)
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{
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first_pass_p = false;
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op1 = GEN_INT (GET_MODE_BITSIZE (mode) - INTVAL (op1));
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binoptab = binoptab == rotl_optab ? rotr_optab : rotl_optab;
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goto retry;
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enum optab_methods next_methods
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= (methods == OPTAB_LIB || methods == OPTAB_LIB_WIDEN
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? OPTAB_WIDEN : methods);
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enum mode_class class;
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enum machine_mode wider_mode;
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rtx temp;
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int commutative_op = 0;
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int shift_op = (binoptab->code == ASHIFT
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|| binoptab->code == ASHIFTRT
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|| binoptab->code == LSHIFTRT
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|| binoptab->code == ROTATE
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|| binoptab->code == ROTATERT);
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rtx entry_last = get_last_insn ();
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rtx last;
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class = GET_MODE_CLASS (mode);
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/* If subtracting an integer constant, convert this into an addition of
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the negated constant. */
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if (binoptab == sub_optab && GET_CODE (op1) == CONST_INT)
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{
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op1 = negate_rtx (mode, op1);
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binoptab = add_optab;
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}
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/* If we are inside an appropriately-short loop and we are optimizing,
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force expensive constants into a register. */
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if (CONSTANT_P (op0) && optimize
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&& rtx_cost (op0, binoptab->code) > COSTS_N_INSNS (1))
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{
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if (GET_MODE (op0) != VOIDmode)
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op0 = convert_modes (mode, VOIDmode, op0, unsignedp);
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op0 = force_reg (mode, op0);
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}
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if (CONSTANT_P (op1) && optimize
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&& ! shift_op && rtx_cost (op1, binoptab->code) > COSTS_N_INSNS (1))
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{
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if (GET_MODE (op1) != VOIDmode)
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op1 = convert_modes (mode, VOIDmode, op1, unsignedp);
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op1 = force_reg (mode, op1);
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}
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/* Record where to delete back to if we backtrack. */
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last = get_last_insn ();
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/* If operation is commutative,
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try to make the first operand a register.
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Even better, try to make it the same as the target.
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Also try to make the last operand a constant. */
|
||||
if (GET_RTX_CLASS (binoptab->code) == RTX_COMM_ARITH
|
||||
|| binoptab == smul_widen_optab
|
||||
|| binoptab == umul_widen_optab
|
||||
|| binoptab == smul_highpart_optab
|
||||
|| binoptab == umul_highpart_optab)
|
||||
{
|
||||
commutative_op = 1;
|
||||
|
||||
if (swap_commutative_operands_with_target (target, op0, op1))
|
||||
{
|
||||
temp = op1;
|
||||
op1 = op0;
|
||||
op0 = temp;
|
||||
}
|
||||
}
|
||||
|
||||
/* If we can do it with a three-operand insn, do so. */
|
||||
|
||||
if (methods != OPTAB_MUST_WIDEN
|
||||
&& binoptab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
|
||||
{
|
||||
temp = expand_binop_directly (mode, binoptab, op0, op1, target,
|
||||
unsignedp, methods, commutative_op, last);
|
||||
if (temp)
|
||||
return temp;
|
||||
}
|
||||
|
||||
/* If we were trying to rotate, and that didn't work, try rotating
|
||||
the other direction before falling back to shifts and bitwise-or. */
|
||||
if (((binoptab == rotl_optab
|
||||
&& rotr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
|
||||
|| (binoptab == rotr_optab
|
||||
&& rotl_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing))
|
||||
&& class == MODE_INT)
|
||||
{
|
||||
optab otheroptab = (binoptab == rotl_optab ? rotr_optab : rotl_optab);
|
||||
rtx newop1;
|
||||
int bits = GET_MODE_BITSIZE (mode);
|
||||
|
||||
if (GET_CODE (op1) == CONST_INT)
|
||||
newop1 = GEN_INT (bits - INTVAL (op1));
|
||||
else if (targetm.shift_truncation_mask (mode) == bits - 1)
|
||||
newop1 = negate_rtx (mode, op1);
|
||||
else
|
||||
newop1 = expand_binop (mode, sub_optab,
|
||||
GEN_INT (bits), op1,
|
||||
NULL_RTX, unsignedp, OPTAB_DIRECT);
|
||||
|
||||
temp = expand_binop_directly (mode, otheroptab, op0, newop1,
|
||||
target, unsignedp, methods,
|
||||
commutative_op, last);
|
||||
if (temp)
|
||||
return temp;
|
||||
}
|
||||
|
||||
/* If this is a multiply, see if we can do a widening operation that
|
||||
|
|
|
|||
|
|
@ -0,0 +1,8 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-mips-options "-O -msmartmips -mno-mips16" } */
|
||||
|
||||
int scaled_indexed_word_load (int a[], int b)
|
||||
{
|
||||
return a[b];
|
||||
}
|
||||
/* { dg-final { scan-assembler "\tlwxs\t" } } */
|
||||
|
|
@ -0,0 +1,8 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-mips-options "-O -msmartmips -mno-mips16" } */
|
||||
|
||||
int rotate_left (unsigned a, unsigned s)
|
||||
{
|
||||
return (a << s) | (a >> (32 - s));
|
||||
}
|
||||
/* { dg-final { scan-assembler "\tror\t" } } */
|
||||
|
|
@ -0,0 +1,8 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-mips-options "-O -msmartmips -mno-mips16" } */
|
||||
|
||||
int rotate_right (unsigned a, unsigned s)
|
||||
{
|
||||
return (a >> s) | (a << (32 - s));
|
||||
}
|
||||
/* { dg-final { scan-assembler "\tror\t" } } */
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-mips-options "-O -msmartmips -mno-mips16" } */
|
||||
|
||||
#define S 13
|
||||
|
||||
int rotate_left_constant (unsigned a)
|
||||
{
|
||||
return (a << S) | (a >> (32 - S));
|
||||
}
|
||||
/* { dg-final { scan-assembler "\tror\t" } } */
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-mips-options "-O -msmartmips -mno-mips16" } */
|
||||
|
||||
#define S 13
|
||||
|
||||
int rotate_right_constant (unsigned a)
|
||||
{
|
||||
return (a >> S) | (a << (32 - S));
|
||||
}
|
||||
/* { dg-final { scan-assembler "\tror\t" } } */
|
||||
Loading…
Reference in New Issue