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Use a URL for FSF address and replace spaces with tab 

* longlong.h: Use a URL instead of an FSF postal address.
	Replace spaces with tab.

From-SVN: r187333
This commit is contained in:
H.J. Lu 2012-05-09 13:36:19 +00:00 committed by H.J. Lu
parent af9059026e
commit 0d03ac1ba7
2 changed files with 22 additions and 18 deletions
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5
libgcc/ChangeLog
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@ -1,3 +1,8 @@
2012-05-09 H.J. Lu <hongjiu.lu@intel.com>
* longlong.h: Use a URL instead of an FSF postal address.
Replace spaces with tab.
2012-05-08 Teresa Johnson <tejohnson@google.com> 2012-05-08 Teresa Johnson <tejohnson@google.com>
* libgcov.c (gcov_clear, __gcov_reset): New functions. * libgcov.c (gcov_clear, __gcov_reset): New functions.

35
libgcc/longlong.h
View File

@ -25,9 +25,8 @@
Lesser General Public License for more details. Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public You should have received a copy of the GNU Lesser General Public
License along with the GNU C Library; if not, write to the Free License along with the GNU C Library; if not, see
Software Foundation, 51 Franklin Street, Fifth Floor, Boston, <http://www.gnu.org/licenses/>. */
MA 02110-1301, USA. */
/* You have to define the following before including this file: /* You have to define the following before including this file:
@ -383,21 +382,21 @@ UDItype __umulsidi3 (USItype, USItype);
do { \ do { \
register SItype __r0 __asm__ ("0"); \ register SItype __r0 __asm__ ("0"); \
register SItype __r1 __asm__ ("1") = (m0); \ register SItype __r1 __asm__ ("1") = (m0); \
\ \
__asm__ ("mr\t%%r0,%3" \ __asm__ ("mr\t%%r0,%3" \
: "=r" (__r0), "=r" (__r1) \ : "=r" (__r0), "=r" (__r1) \
: "r" (__r1), "r" (m1)); \ : "r" (__r1), "r" (m1)); \
(xh) = __r0; (xl) = __r1; \ (xh) = __r0; (xl) = __r1; \
} while (0) } while (0)
#define sdiv_qrnnd(q, r, n1, n0, d) \ #define sdiv_qrnnd(q, r, n1, n0, d) \
do { \ do { \
register SItype __r0 __asm__ ("0") = (n1); \ register SItype __r0 __asm__ ("0") = (n1); \
register SItype __r1 __asm__ ("1") = (n0); \ register SItype __r1 __asm__ ("1") = (n0); \
\ \
__asm__ ("dr\t%%r0,%4" \ __asm__ ("dr\t%%r0,%4" \
: "=r" (__r0), "=r" (__r1) \ : "=r" (__r0), "=r" (__r1) \
: "r" (__r0), "r" (__r1), "r" (d)); \ : "r" (__r0), "r" (__r1), "r" (d)); \
(q) = __r1; (r) = __r0; \ (q) = __r1; (r) = __r0; \
} while (0) } while (0)
#endif /* __zarch__ */ #endif /* __zarch__ */
@ -840,9 +839,9 @@ UDItype __umulsidi3 (USItype, USItype);
#define count_trailing_zeros(count,x) \ #define count_trailing_zeros(count,x) \
do { \ do { \
__asm__ ("ffsd %2,%0" \ __asm__ ("ffsd %2,%0" \
: "=r" ((USItype) (count)) \ : "=r" ((USItype) (count)) \
: "0" ((USItype) 0), \ : "0" ((USItype) 0), \
"r" ((USItype) (x))); \ "r" ((USItype) (x))); \
} while (0) } while (0)
#endif /* __ns32000__ */ #endif /* __ns32000__ */
@ -858,7 +857,7 @@ UDItype __umulsidi3 (USItype, USItype);
|| defined (__ppc__) /* Darwin */ \ || defined (__ppc__) /* Darwin */ \
|| (defined (PPC) && ! defined (CPU_FAMILY)) /* gcc 2.7.x GNU&SysV */ \ || (defined (PPC) && ! defined (CPU_FAMILY)) /* gcc 2.7.x GNU&SysV */ \
|| (defined (PPC) && defined (CPU_FAMILY) /* VxWorks */ \ || (defined (PPC) && defined (CPU_FAMILY) /* VxWorks */ \
&& CPU_FAMILY == PPC) \ && CPU_FAMILY == PPC) \
) && W_TYPE_SIZE == 32 ) && W_TYPE_SIZE == 32
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
do { \ do { \
@ -899,7 +898,7 @@ UDItype __umulsidi3 (USItype, USItype);
|| defined (__ppc__) \ || defined (__ppc__) \
|| (defined (PPC) && ! defined (CPU_FAMILY)) /* gcc 2.7.x GNU&SysV */ \ || (defined (PPC) && ! defined (CPU_FAMILY)) /* gcc 2.7.x GNU&SysV */ \
|| (defined (PPC) && defined (CPU_FAMILY) /* VxWorks */ \ || (defined (PPC) && defined (CPU_FAMILY) /* VxWorks */ \
&& CPU_FAMILY == PPC) && CPU_FAMILY == PPC)
#define umul_ppmm(ph, pl, m0, m1) \ #define umul_ppmm(ph, pl, m0, m1) \
do { \ do { \
USItype __m0 = (m0), __m1 = (m1); \ USItype __m0 = (m0), __m1 = (m1); \
@ -1067,7 +1066,7 @@ UDItype __umulsidi3 (USItype, USItype);
#define udiv_qrnnd(q, r, n1, n0, d) \ #define udiv_qrnnd(q, r, n1, n0, d) \
do { \ do { \
extern UWtype __udiv_qrnnd_16 (UWtype, UWtype) \ extern UWtype __udiv_qrnnd_16 (UWtype, UWtype) \
__attribute__ ((visibility ("hidden"))); \ __attribute__ ((visibility ("hidden"))); \
/* r0: rn r1: qn */ /* r0: n1 r4: n0 r5: d r6: d1 */ /* r2: __m */ \ /* r0: rn r1: qn */ /* r0: n1 r4: n0 r5: d r6: d1 */ /* r2: __m */ \
__asm__ ( \ __asm__ ( \
"mov%M4 %4,r5\n" \ "mov%M4 %4,r5\n" \
@ -1202,8 +1201,8 @@ UDItype __umulsidi3 (USItype, USItype);
#define count_leading_zeros(count, x) \ #define count_leading_zeros(count, x) \
do { \ do { \
__asm__ ("scan %1,1,%0" \ __asm__ ("scan %1,1,%0" \
: "=r" ((USItype) (count)) \ : "=r" ((USItype) (count)) \
: "r" ((USItype) (x))); \ : "r" ((USItype) (x))); \
} while (0) } while (0)
/* Early sparclites return 63 for an argument of 0, but they warn that future /* Early sparclites return 63 for an argument of 0, but they warn that future
implementations might change this. Therefore, leave COUNT_LEADING_ZEROS_0 implementations might change this. Therefore, leave COUNT_LEADING_ZEROS_0