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Add patterns for v8hf vectorization. 

2025-10-13  Michael Meissner  <meissner@linux.ibm.com>

gcc/

	* config/rs6000/altivec.md (altivec_vsplth_internal_v8h): New insn.
	(altivec_lvehf): Likewise.
This commit is contained in:
Michael Meissner 2025-10-14 01:59:40 -04:00
parent 030926e2a5
commit 188e8eb838
1 changed files with 25 additions and 0 deletions
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25
gcc/config/rs6000/altivec.md
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@ -2402,6 +2402,22 @@
}
[(set_attr "type" "vecperm")])
(define_insn "*altivec_vsplth_internal_v8hx"
[(set (match_operand:V8HF 0 "register_operand" "=v")
(vec_duplicate:V8HF
(vec_select:HF (match_operand:V8HF 1 "register_operand" "v")
(parallel
[(match_operand:QI 2 "const_0_to_7_operand" "")]))))]
"TARGET_ALTIVEC"
{
if (!BYTES_BIG_ENDIAN)
operands[2] = GEN_INT (7 - INTVAL (operands[2]));
return "vsplth %0,%1,%2";
}
[(set_attr "type" "vecperm")])
(define_insn "altivec_vsplth_direct"
[(set (match_operand:V8HI 0 "register_operand" "=v")
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
@ -3130,6 +3146,15 @@
"lvewx %0,%y1"
[(set_attr "type" "vecload")])
(define_insn "*altivec_lvehf"
[(parallel
[(set (match_operand:V8HF 0 "register_operand" "=v")
(match_operand:V8HF 1 "memory_operand" "Z"))
(unspec [(const_int 0)] UNSPEC_LVE)])]
"TARGET_ALTIVEC"
"lvehx %0,%y1"
[(set_attr "type" "vecload")])
(define_insn "altivec_lvxl_<mode>"
[(parallel
[(set (match_operand:VM2 0 "register_operand" "=v")