mirror of git://gcc.gnu.org/git/gcc.git
altivec.md (p8_vmrgow): Add support for V2DI, V2DF, V4SI, V4SF types.
gcc/ChangeLog: 2018-01-09 Carl Love <cel@us.ibm.com> * config/rs6002/altivec.md (p8_vmrgow): Add support for V2DI, V2DF, V4SI, V4SF types. (p8_vmrgew): Add support for V2DI, V2DF, V4SF types. * config/rs6000/rs6000-builtin.def: Add definitions for FLOAT2_V2DF, VMRGEW_V2DI, VMRGEW_V2DF, VMRGEW_V4SF, VMRGOW_V4SI, VMRGOW_V4SF, VMRGOW_V2DI, VMRGOW_V2DF. Remove definition for VMRGOW. * config/rs6000/rs6000-c.c (VSX_BUILTIN_VEC_FLOAT2, P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VEC_VMRGOW): Add definitions. * config/rs6000/rs6000-protos.h: Add extern defition for rs6000_generate_float2_double_code. * config/rs6000/rs6000.c (rs6000_generate_float2_double_code): Add function. * config/rs6000/vsx.md (vsx_xvcdpsp): Add define_insn. (float2_v2df): Add define_expand. gcc/testsuite/ChangeLog: 2017-01-09 Carl Love <cel@us.ibm.com> * gcc.target/powerpc/builtins-1.c (main): Add tests for vec_mergee and vec_mergeo builtins with float, double, long long, unsigned long long, bool long long arguments. * gcc.target/powerpc/builtins-3-runnable.c (main): Add test for vec_float2 with double arguments. * gcc.target/powerpc/builtins-mergew-mergow.c: New runable test for the vec_mergew and vec_mergow builtins. From-SVN: r256395
This commit is contained in:
Carl Love
Carl Love
parent
594d0e51b7
commit
19d22f7c90
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@ -1,3 +1,20 @@
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2018-01-09 Carl Love <cel@us.ibm.com>
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* config/rs6002/altivec.md (p8_vmrgow): Add support for V2DI, V2DF,
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V4SI, V4SF types.
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(p8_vmrgew): Add support for V2DI, V2DF, V4SF types.
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* config/rs6000/rs6000-builtin.def: Add definitions for FLOAT2_V2DF,
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VMRGEW_V2DI, VMRGEW_V2DF, VMRGEW_V4SF, VMRGOW_V4SI, VMRGOW_V4SF,
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VMRGOW_V2DI, VMRGOW_V2DF. Remove definition for VMRGOW.
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* config/rs6000/rs6000-c.c (VSX_BUILTIN_VEC_FLOAT2,
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P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VEC_VMRGOW): Add definitions.
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* config/rs6000/rs6000-protos.h: Add extern defition for
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rs6000_generate_float2_double_code.
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* config/rs6000/rs6000.c (rs6000_generate_float2_double_code): Add
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function.
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* config/rs6000/vsx.md (vsx_xvcdpsp): Add define_insn.
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(float2_v2df): Add define_expand.
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2018-01-09 Uros Bizjak <ubizjak@gmail.com>
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PR target/83628
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@ -1318,6 +1318,24 @@
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}
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[(set_attr "type" "vecperm")])
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;; Power8 vector merge two V2DF/V2DI even words to V2DF
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(define_expand "p8_vmrgew_<mode>"
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[(use (match_operand:VSX_D 0 "vsx_register_operand"))
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(use (match_operand:VSX_D 1 "vsx_register_operand"))
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(use (match_operand:VSX_D 2 "vsx_register_operand"))]
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"VECTOR_MEM_VSX_P (<MODE>mode)"
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{
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rtvec v;
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rtx x;
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v = gen_rtvec (2, GEN_INT (0), GEN_INT (2));
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x = gen_rtx_VEC_CONCAT (<VS_double>mode, operands[1], operands[2]);
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x = gen_rtx_VEC_SELECT (<MODE>mode, x, gen_rtx_PARALLEL (VOIDmode, v));
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emit_insn (gen_rtx_SET (operands[0], x));
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DONE;
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})
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;; Power8 vector merge two V4SF/V4SI even words to V4SF
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(define_insn "p8_vmrgew_<mode>"
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[(set (match_operand:VSX_W 0 "register_operand" "=v")
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@ -1336,12 +1354,12 @@
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}
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[(set_attr "type" "vecperm")])
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(define_insn "p8_vmrgow"
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[(set (match_operand:V4SI 0 "register_operand" "=v")
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(vec_select:V4SI
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(vec_concat:V8SI
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(match_operand:V4SI 1 "register_operand" "v")
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(match_operand:V4SI 2 "register_operand" "v"))
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(define_insn "p8_vmrgow_<mode>"
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[(set (match_operand:VSX_W 0 "register_operand" "=v")
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(vec_select:VSX_W
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(vec_concat:<VS_double>
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(match_operand:VSX_W 1 "register_operand" "v")
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(match_operand:VSX_W 2 "register_operand" "v"))
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(parallel [(const_int 1) (const_int 5)
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(const_int 3) (const_int 7)])))]
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"TARGET_P8_VECTOR"
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@ -1353,6 +1371,23 @@
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}
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[(set_attr "type" "vecperm")])
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(define_expand "p8_vmrgow_<mode>"
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[(use (match_operand:VSX_D 0 "vsx_register_operand"))
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(use (match_operand:VSX_D 1 "vsx_register_operand"))
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(use (match_operand:VSX_D 2 "vsx_register_operand"))]
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"VECTOR_MEM_VSX_P (<MODE>mode)"
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{
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rtvec v;
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rtx x;
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v = gen_rtvec (2, GEN_INT (1), GEN_INT (3));
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x = gen_rtx_VEC_CONCAT (<VS_double>mode, operands[1], operands[2]);
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x = gen_rtx_VEC_SELECT (<MODE>mode, x, gen_rtx_PARALLEL (VOIDmode, v));
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emit_insn (gen_rtx_SET (operands[0], x));
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DONE;
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})
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(define_insn "p8_vmrgew_<mode>_direct"
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[(set (match_operand:VSX_W 0 "register_operand" "=v")
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(unspec:VSX_W [(match_operand:VSX_W 1 "register_operand" "v")
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@ -1650,6 +1650,7 @@ BU_VSX_2 (CMPLE_U16QI, "cmple_u16qi", CONST, vector_ngtuv16qi)
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BU_VSX_2 (CMPLE_U8HI, "cmple_u8hi", CONST, vector_ngtuv8hi)
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BU_VSX_2 (CMPLE_U4SI, "cmple_u4si", CONST, vector_ngtuv4si)
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BU_VSX_2 (CMPLE_U2DI, "cmple_u2di", CONST, vector_ngtuv2di)
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BU_VSX_2 (FLOAT2_V2DF, "float2_v2df", CONST, float2_v2df)
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BU_VSX_2 (FLOAT2_V2DI, "float2_v2di", CONST, float2_v2di)
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BU_VSX_2 (UNS_FLOAT2_V2DI, "uns_float2_v2di", CONST, uns_float2_v2di)
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@ -1924,8 +1925,14 @@ BU_P8V_AV_2 (VMINSD, "vminsd", CONST, sminv2di3)
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BU_P8V_AV_2 (VMAXSD, "vmaxsd", CONST, smaxv2di3)
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BU_P8V_AV_2 (VMINUD, "vminud", CONST, uminv2di3)
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BU_P8V_AV_2 (VMAXUD, "vmaxud", CONST, umaxv2di3)
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BU_P8V_AV_2 (VMRGEW_V2DI, "vmrgew_v2di", CONST, p8_vmrgew_v2di)
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BU_P8V_AV_2 (VMRGEW_V2DF, "vmrgew_v2df", CONST, p8_vmrgew_v2df)
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BU_P8V_AV_2 (VMRGEW_V4SI, "vmrgew_v4si", CONST, p8_vmrgew_v4si)
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BU_P8V_AV_2 (VMRGOW, "vmrgow", CONST, p8_vmrgow)
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BU_P8V_AV_2 (VMRGEW_V4SF, "vmrgew_v4sf", CONST, p8_vmrgew_v4sf)
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BU_P8V_AV_2 (VMRGOW_V4SI, "vmrgow_v4si", CONST, p8_vmrgow_v4si)
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BU_P8V_AV_2 (VMRGOW_V4SF, "vmrgow_v4sf", CONST, p8_vmrgow_v4sf)
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BU_P8V_AV_2 (VMRGOW_V2DI, "vmrgow_v2di", CONST, p8_vmrgow_v2di)
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BU_P8V_AV_2 (VMRGOW_V2DF, "vmrgow_v2df", CONST, p8_vmrgow_v2df)
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BU_P8V_AV_2 (VBPERMQ, "vbpermq", CONST, altivec_vbpermq)
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BU_P8V_AV_2 (VBPERMQ2, "vbpermq2", CONST, altivec_vbpermq2)
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BU_P8V_AV_2 (VPKUDUM, "vpkudum", CONST, altivec_vpkudum)
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@ -1531,6 +1531,8 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
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RS6000_BTI_V4SF, RS6000_BTI_V4SI, 0, 0 },
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{ VSX_BUILTIN_VEC_FLOAT, VSX_BUILTIN_XVCVUXWSP_V4SF,
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RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, 0, 0 },
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{ VSX_BUILTIN_VEC_FLOAT2, VSX_BUILTIN_FLOAT2_V2DF,
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RS6000_BTI_V4SF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
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{ VSX_BUILTIN_VEC_FLOAT2, VSX_BUILTIN_FLOAT2_V2DI,
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RS6000_BTI_V4SF, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
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{ VSX_BUILTIN_VEC_FLOAT2, VSX_BUILTIN_UNS_FLOAT2_V2DI,
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@ -5520,6 +5522,17 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
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RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
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RS6000_BTI_unsigned_V2DI, 0 },
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{ P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V2DI,
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RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
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{ P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V2DI,
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RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
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RS6000_BTI_unsigned_V2DI, 0 },
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{ P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V2DI,
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RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
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{ P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V4SF,
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RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
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{ P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V2DF,
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RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
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{ P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V4SI,
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RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
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{ P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V4SI,
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@ -5528,13 +5541,26 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
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{ P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V4SI,
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RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
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{ P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW,
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{ P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V4SI,
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RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
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{ P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW,
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{ P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V4SI,
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RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
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RS6000_BTI_unsigned_V4SI, 0 },
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{ P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW,
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{ P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V4SI,
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RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
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{ P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V2DI,
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RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
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{ P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V2DI,
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RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
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{ P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V2DI,
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RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
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RS6000_BTI_unsigned_V2DI, 0 },
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{ P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V2DI,
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RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
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{ P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V2DF,
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RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
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{ P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V4SF,
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RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
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{ P8V_BUILTIN_VEC_VPMSUM, P8V_BUILTIN_VPMSUMB,
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RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI,
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@ -71,6 +71,7 @@ extern void rs6000_expand_extract_even (rtx, rtx, rtx);
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extern void rs6000_expand_interleave (rtx, rtx, rtx, bool);
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extern void rs6000_scale_v2df (rtx, rtx, int);
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extern void rs6000_generate_float2_code (bool, rtx, rtx, rtx);
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extern void rs6000_generate_float2_double_code (rtx, rtx, rtx);
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extern void rs6000_generate_vsigned2_code (bool, rtx, rtx, rtx);
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extern int expand_block_clear (rtx[]);
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extern int expand_block_move (rtx[]);
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@ -39439,6 +39439,43 @@ rs6000_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
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*update = build2 (COMPOUND_EXPR, void_type_node, update_mffs, update_mtfsf);
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}
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void
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rs6000_generate_float2_double_code (rtx dst, rtx src1, rtx src2)
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{
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rtx rtx_tmp0, rtx_tmp1, rtx_tmp2, rtx_tmp3;
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rtx_tmp0 = gen_reg_rtx (V2DFmode);
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rtx_tmp1 = gen_reg_rtx (V2DFmode);
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/* The destination of the vmrgew instruction layout is:
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rtx_tmp2[0] rtx_tmp3[0] rtx_tmp2[1] rtx_tmp3[0].
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Setup rtx_tmp0 and rtx_tmp1 to ensure the order of the elements after the
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vmrgew instruction will be correct. */
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if (VECTOR_ELT_ORDER_BIG)
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{
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emit_insn (gen_vsx_xxpermdi_v2df_be (rtx_tmp0, src1, src2,
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GEN_INT (0)));
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emit_insn (gen_vsx_xxpermdi_v2df_be (rtx_tmp1, src1, src2,
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GEN_INT (3)));
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}
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else
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{
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emit_insn (gen_vsx_xxpermdi_v2df (rtx_tmp0, src1, src2, GEN_INT (3)));
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emit_insn (gen_vsx_xxpermdi_v2df (rtx_tmp1, src1, src2, GEN_INT (0)));
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}
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rtx_tmp2 = gen_reg_rtx (V4SFmode);
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rtx_tmp3 = gen_reg_rtx (V4SFmode);
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emit_insn (gen_vsx_xvcdpsp (rtx_tmp2, rtx_tmp0));
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emit_insn (gen_vsx_xvcdpsp (rtx_tmp3, rtx_tmp1));
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if (VECTOR_ELT_ORDER_BIG)
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emit_insn (gen_p8_vmrgew_v4sf (dst, rtx_tmp2, rtx_tmp3));
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else
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emit_insn (gen_p8_vmrgew_v4sf (dst, rtx_tmp3, rtx_tmp2));
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}
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void
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rs6000_generate_float2_code (bool signed_convert, rtx dst, rtx src1, rtx src2)
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{
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@ -372,6 +372,7 @@
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UNSPEC_VSX_XVCVSXDDP
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UNSPEC_VSX_XVCVUXDDP
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UNSPEC_VSX_XVCVDPSXDS
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UNSPEC_VSX_XVCDPSP
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UNSPEC_VSX_XVCVDPUXDS
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UNSPEC_VSX_SIGN_EXTEND
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UNSPEC_VSX_XVCVSPSXWS
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@ -2171,6 +2172,14 @@
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"xvcvuxdsp %x0,%x1"
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[(set_attr "type" "vecdouble")])
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(define_insn "vsx_xvcdpsp"
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[(set (match_operand:V4SF 0 "vsx_register_operand" "=wd,?wa")
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(unspec:V4SF [(match_operand:V2DF 1 "vsx_register_operand" "wf,wa")]
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UNSPEC_VSX_XVCDPSP))]
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"VECTOR_UNIT_VSX_P (V2DFmode)"
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"xvcvdpsp %x0,%x1"
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[(set_attr "type" "vecdouble")])
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;; Convert from 32-bit to 64-bit types
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;; Provide both vector and scalar targets
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(define_insn "vsx_xvcvsxwdp"
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@ -2237,6 +2246,24 @@
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"xvcvuxwsp %x0,%x1"
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[(set_attr "type" "vecfloat")])
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;; Generate float2 double
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;; convert two double to float
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(define_expand "float2_v2df"
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[(use (match_operand:V4SF 0 "register_operand" "=wa"))
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(use (match_operand:V2DF 1 "register_operand" "wa"))
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(use (match_operand:V2DF 2 "register_operand" "wa"))]
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"VECTOR_UNIT_VSX_P (V4SFmode)"
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{
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rtx rtx_src1, rtx_src2, rtx_dst;
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rtx_dst = operands[0];
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rtx_src1 = operands[1];
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rtx_src2 = operands[2];
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rs6000_generate_float2_double_code (rtx_dst, rtx_src1, rtx_src2);
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DONE;
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})
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;; Generate float2
|
||||
;; convert two long long signed ints to float
|
||||
(define_expand "float2_v2di"
|
||||
|
|
|
|||
|
|
@ -1,3 +1,13 @@
|
|||
2017-01-09 Carl Love <cel@us.ibm.com>
|
||||
|
||||
* gcc.target/powerpc/builtins-1.c (main): Add tests for vec_mergee and
|
||||
vec_mergeo builtins with float, double, long long, unsigned long long,
|
||||
bool long long arguments.
|
||||
* gcc.target/powerpc/builtins-3-runnable.c (main): Add test for
|
||||
vec_float2 with double arguments.
|
||||
* gcc.target/powerpc/builtins-mergew-mergow.c: New runable test for the
|
||||
vec_mergew and vec_mergow builtins.
|
||||
|
||||
2018-01-09 Steven G. Kargl <kargl@gcc.gnu.org>
|
||||
|
||||
PR fortran/83742
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
/* This test is included into builtins-1-be.c and builtins-1-le.c to test on
|
||||
Big Endian and Little Endian machines. */
|
||||
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
vector double y = { 2.0, 4.0 };
|
||||
|
|
@ -14,7 +14,7 @@ int main ()
|
|||
vector float fc = vec_cpsgn (fa, fb);
|
||||
vector float fe = vec_mergeh (fa, fb);
|
||||
vector float ff = vec_mergel (fa, fb);
|
||||
|
||||
|
||||
vector double da = {1.0, 2.0};
|
||||
vector double db = {-2.0, -3.0};
|
||||
vector double dz = vec_and (da, db);
|
||||
|
|
@ -36,7 +36,7 @@ int main ()
|
|||
vector long long lg = vec_andc (la, lb);
|
||||
vector long long lh = vec_andc (la, ld);
|
||||
vector long long li = vec_andc (ld, lb);
|
||||
|
||||
|
||||
vector unsigned long long ug = vec_andc (ua, ub);
|
||||
vector unsigned long long uh = vec_andc (ua, ud);
|
||||
vector unsigned long long ui = vec_andc (ud, ub);
|
||||
|
|
@ -176,7 +176,7 @@ int main ()
|
|||
vector unsigned short usc = vec_cntlz (usa);
|
||||
vector unsigned short uscd = vec_mergeh (usa, usb);
|
||||
vector unsigned short usce = vec_mergel (usa, usb);
|
||||
|
||||
|
||||
vector signed char sca = {-4, 3, -9, 15, -31, 31, 0, 0,
|
||||
1, 117, -36, 99, 98, 97, 96, 95};
|
||||
vector signed char scb = vec_cntlz (sca);
|
||||
|
|
@ -199,9 +199,15 @@ int main ()
|
|||
vector unsigned long long u4 = vec_splat (u2, 1);
|
||||
vector bool long long l5 = vec_splat (ld, 0);
|
||||
vector bool long long l6 = vec_splat (ld, 1);
|
||||
vector bool long long l10 = vec_mergee (ld, ld);
|
||||
vector bool long long l11 = vec_mergeo (ld, ld);
|
||||
|
||||
vector long long l7 = vec_div (l3, l4);
|
||||
vector unsigned long long u5 = vec_div (u3, u4);
|
||||
vector long long l12 = vec_mergee (la, lb);
|
||||
vector long long l13 = vec_mergeo (la, lb);
|
||||
vector unsigned long long u8 = vec_mergee (u3, u4);
|
||||
vector unsigned long long u9 = vec_mergeo (u3, u4);
|
||||
|
||||
vector long long l8 = vec_mul (l3, l4);
|
||||
vector unsigned long long u6 = vec_mul (u3, u4);
|
||||
|
|
@ -213,5 +219,11 @@ int main ()
|
|||
vector unsigned long long u7 = vec_ctu (di, 2);
|
||||
vector unsigned int usz = vec_ctu (fa, 0x1F);
|
||||
|
||||
vector float f1 = vec_mergee (fa, fb);
|
||||
vector float f2 = vec_mergeo (fa, fb);
|
||||
|
||||
vector double d1 = vec_mergee (da, db);
|
||||
vector double d2 = vec_mergeo (da, db);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -266,6 +266,10 @@ int main()
|
|||
vec_flt_result = vec_float2 (vec_ll_uns_int0, vec_ll_uns_int1);
|
||||
test_result_sp(ALL, vec_flt_result, vec_flt_expected);
|
||||
|
||||
vec_flt_expected = (vector float){34.0, 97.0, 214.0, -5.5};
|
||||
vec_flt_result = vec_float2 (vec_dble0, vec_dble1);
|
||||
test_result_sp(ALL, vec_flt_result, vec_flt_expected);
|
||||
|
||||
/* conversion of even words in double precision vector to single precision vector */
|
||||
vec_flt_expected = (vector float){-12.00, 00.00, -12345678901234.00, 0.00};
|
||||
vec_flt_result = vec_floate (vec_ll_int0);
|
||||
|
|
|
|||
|
|
@ -0,0 +1,263 @@
|
|||
/* { dg-do run } */
|
||||
/* { dg-require-effective-target vsx_hw } */
|
||||
/* { dg-options "-maltivec -mvsx" } */
|
||||
|
||||
#include <altivec.h> // vector
|
||||
#include <stdlib.h>
|
||||
|
||||
#ifdef DEBUG
|
||||
#include <stdio.h>
|
||||
#endif
|
||||
|
||||
void abort (void);
|
||||
|
||||
int main() {
|
||||
vector signed int vec_si_arg1, vec_si_arg2;
|
||||
vector signed int vec_si_expected, vec_si_result;
|
||||
vector unsigned int vec_ui_arg1, vec_ui_arg2;
|
||||
vector unsigned int vec_ui_expected, vec_ui_result;
|
||||
vector signed long long vec_sll_arg1, vec_sll_arg2;
|
||||
vector signed long long vec_sll_expected, vec_sll_result;
|
||||
vector unsigned long long vec_ull_arg1, vec_ull_arg2;
|
||||
vector unsigned long long vec_ull_expected, vec_ull_result;
|
||||
vector bool long long vec_bll_arg1, vec_bll_arg2;
|
||||
vector bool long long vec_bll_expected, vec_bll_result;
|
||||
vector float vec_f_arg1, vec_f_arg2;
|
||||
vector float vec_f_expected, vec_f_result;
|
||||
vector double vec_d_arg1, vec_d_arg2;
|
||||
vector double vec_d_expected, vec_d_result;
|
||||
int i;
|
||||
unsigned long long int value;
|
||||
|
||||
/* Tests for vec_mergeo, Merges the odd-numbered halves of two vectors. */
|
||||
vec_si_arg1 = (vector int){-100, -101, 102, 103};
|
||||
vec_si_arg2 = (vector int){200, 201, 202, 203};
|
||||
|
||||
vec_si_result = vec_mergeo (vec_si_arg1, vec_si_arg2);
|
||||
|
||||
vec_si_expected = (vector int){-101, 201, 103, 203};
|
||||
|
||||
for (i = 0; i < 4; i++)
|
||||
if (vec_si_result[i] != vec_si_expected[i])
|
||||
#ifdef DEBUG
|
||||
printf("ERROR vec_mergeo(): vec_si_result[%d] = %d, vec_si_expected[%d] = %d\n",
|
||||
i, vec_si_result[i], i, vec_si_expected[i]);
|
||||
#else
|
||||
abort();
|
||||
#endif
|
||||
|
||||
vec_ui_arg1 = (vector unsigned int){100, 101, 102, 103};
|
||||
vec_ui_arg2 = (vector unsigned int){200, 201, 202, 203};
|
||||
|
||||
vec_ui_result = vec_mergeo (vec_ui_arg1, vec_ui_arg2);
|
||||
|
||||
vec_ui_expected = (vector unsigned int){101, 201, 103, 203};
|
||||
|
||||
for (i = 0; i < 4; i++)
|
||||
if (vec_ui_result[i] != vec_ui_expected[i])
|
||||
#ifdef DEBUG
|
||||
printf("ERROR vec_mergeo(): vec_ui_result[%d] = %d, vec_ui_expected[%d] = %d\n",
|
||||
i, vec_ui_result[i], i, vec_ui_expected[i]);
|
||||
#else
|
||||
abort();
|
||||
#endif
|
||||
|
||||
vec_sll_arg1 = (vector long long int){-300, -301};
|
||||
vec_sll_arg2 = (vector long long int){400, 401};
|
||||
|
||||
vec_sll_result = vec_mergeo (vec_sll_arg1, vec_sll_arg2);
|
||||
|
||||
vec_sll_expected = (vector long long int){-301, 401};
|
||||
|
||||
for (i = 0; i < 2; i++)
|
||||
if (vec_sll_result[i] != vec_sll_expected[i])
|
||||
#ifdef DEBUG
|
||||
printf("ERROR vec_mergeo(): vec_sll_result[%d] = %lld, vec_sll_expected[%d] = %lld\n",
|
||||
i, (long long int)vec_sll_result[i],
|
||||
i, (long long int)vec_sll_expected[i]);
|
||||
#else
|
||||
abort();
|
||||
#endif
|
||||
|
||||
vec_ull_arg1 = (vector unsigned long long int){500, 501};
|
||||
vec_ull_arg2 = (vector unsigned long long int){600, 601};
|
||||
|
||||
vec_ull_result = vec_mergeo (vec_ull_arg1, vec_ull_arg2);
|
||||
|
||||
vec_ull_expected = (vector unsigned long long int){501, 601};
|
||||
|
||||
for (i = 0; i < 2; i++)
|
||||
if (vec_ull_result[i] != vec_ull_expected[i])
|
||||
#ifdef DEBUG
|
||||
printf("ERROR vec_mergeo(): vec_ull_result[%d] = %lld, vec_ull_expected[%d] = %lld\n",
|
||||
i, (unsigned long long int)vec_ull_result[i],
|
||||
i, (unsigned long long int)vec_ull_expected[i]);
|
||||
#else
|
||||
abort();
|
||||
#endif
|
||||
|
||||
vec_bll_arg1 = (vector bool long long){0, 0};
|
||||
vec_bll_arg2 = (vector bool long long){1, 1};
|
||||
|
||||
vec_bll_result = vec_mergeo (vec_bll_arg1, vec_bll_arg2);
|
||||
|
||||
vec_bll_expected = (vector bool long long){0, 1};
|
||||
|
||||
for (i = 0; i < 2; i++)
|
||||
if (vec_bll_result[i] != vec_bll_expected[i])
|
||||
#ifdef DEBUG
|
||||
printf("ERROR vec_mergeo(): vec_bll_result[%d] = %lld, vec_bll_expected[%d] = %lld\n",
|
||||
i, vec_ull_result[i],
|
||||
i, vec_ull_expected[i]);
|
||||
#else
|
||||
abort();
|
||||
#endif
|
||||
|
||||
vec_f_arg1 = (vector float){100.0, 101.1, 102.2, 103.3};
|
||||
vec_f_arg2 = (vector float){200.0, 201.1, 202.2, 203.3};
|
||||
|
||||
vec_f_result = vec_mergeo (vec_f_arg1, vec_f_arg2);
|
||||
|
||||
vec_f_expected = (vector float){101.1, 201.1, 103.3, 203.3};
|
||||
|
||||
for (i = 0; i < 4; i++)
|
||||
if (vec_f_result[i] != vec_f_expected[i])
|
||||
#ifdef DEBUG
|
||||
printf("ERROR vec_mergeo(): vec_f_result[%d] = %f, vec_f_expected[%d] = %f\n",
|
||||
i, vec_f_result[i], i, vec_f_expected[i]);
|
||||
#else
|
||||
abort();
|
||||
#endif
|
||||
|
||||
vec_d_arg1 = (vector double){300.0, 301.1};
|
||||
vec_d_arg2 = (vector double){400.0, 401.1};
|
||||
|
||||
vec_d_result = vec_mergeo (vec_d_arg1, vec_d_arg2);
|
||||
|
||||
vec_d_expected = (vector double){301.1, 401.1};
|
||||
|
||||
for (i = 0; i < 2; i++)
|
||||
if (vec_d_result[i] != vec_d_expected[i])
|
||||
#ifdef DEBUG
|
||||
printf("ERROR vec_mergeo(): vec_d_result[%d] = %f, vec_d_expected[%d] = %f\n",
|
||||
i, vec_d_result[i], i, vec_d_expected[i]);
|
||||
#else
|
||||
abort();
|
||||
#endif
|
||||
|
||||
/* Tests for vec_mergee, Merges the even-numbered halves of two vectors. */
|
||||
vec_si_arg1 = (vector int){-100, -101, 102, 103};
|
||||
vec_si_arg2 = (vector int){200, 201, 202, 203};
|
||||
|
||||
vec_si_result = vec_mergee (vec_si_arg1, vec_si_arg2);
|
||||
|
||||
vec_si_expected = (vector int){-100, 200, 102, 202};
|
||||
|
||||
for (i = 0; i < 4; i++)
|
||||
if (vec_si_result[i] != vec_si_expected[i])
|
||||
#ifdef DEBUG
|
||||
printf("ERROR vec_mergee(): vec_si_result[%d] = %d, vec_si_expected[%d] = %d\n",
|
||||
i, vec_si_result[i], i, vec_si_expected[i]);
|
||||
#else
|
||||
abort();
|
||||
#endif
|
||||
|
||||
vec_ui_arg1 = (vector unsigned int){100, 101, 102, 103};
|
||||
vec_ui_arg2 = (vector unsigned int){200, 201, 202, 203};
|
||||
|
||||
vec_ui_result = vec_mergee (vec_ui_arg1, vec_ui_arg2);
|
||||
|
||||
vec_ui_expected = (vector unsigned int){100, 200, 102, 202};
|
||||
|
||||
for (i = 0; i < 4; i++)
|
||||
if (vec_ui_result[i] != vec_ui_expected[i])
|
||||
#ifdef DEBUG
|
||||
printf("ERROR vec_mergee(): vec_ui_result[%d] = %d, vec_ui_expected[%d] = %d\n",
|
||||
i, vec_ui_result[i], i, vec_ui_expected[i]);
|
||||
#else
|
||||
abort();
|
||||
#endif
|
||||
|
||||
vec_sll_arg1 = (vector signed long long int){-300, -301};
|
||||
vec_sll_arg2 = (vector signed long long int){400, 401};
|
||||
|
||||
vec_sll_result = vec_mergee (vec_sll_arg1, vec_sll_arg2);
|
||||
|
||||
vec_sll_expected = (vector signed long long int){-300, 400};
|
||||
|
||||
for (i = 0; i < 2; i++)
|
||||
if (vec_sll_result[i] != vec_sll_expected[i])
|
||||
#ifdef DEBUG
|
||||
printf("ERROR vec_mergee(): vec_sll_result[%d] = %lld, vec_sll_expected[%d] = %lld\n",
|
||||
i, (signed long long int)vec_sll_result[i],
|
||||
i, (signed long long int)vec_sll_expected[i]);
|
||||
#else
|
||||
abort();
|
||||
#endif
|
||||
|
||||
vec_ull_arg1 = (vector unsigned long long int){500, 501};
|
||||
vec_ull_arg2 = (vector unsigned long long int){600, 601};
|
||||
|
||||
vec_ull_result = vec_mergee (vec_ull_arg1, vec_ull_arg2);
|
||||
|
||||
vec_ull_expected = (vector unsigned long long int){500, 600};
|
||||
|
||||
for (i = 0; i < 2; i++)
|
||||
if (vec_ull_result[i] != vec_ull_expected[i])
|
||||
#ifdef DEBUG
|
||||
printf("ERROR vec_mergee(): vec_ull_result[%d] = %lld, vec_ull_expected[%d] = %lld\n",
|
||||
i, (unsigned long long int)vec_ull_result[i],
|
||||
i, (unsigned long long int)vec_ull_expected[i]);
|
||||
#else
|
||||
abort();
|
||||
#endif
|
||||
|
||||
vec_bll_arg1 = (vector bool long long){0, 0};
|
||||
vec_bll_arg2 = (vector bool long long){1, 1};
|
||||
|
||||
vec_bll_result = vec_mergee (vec_bll_arg1, vec_bll_arg2);
|
||||
|
||||
vec_bll_expected = (vector bool long long){0, 1};
|
||||
|
||||
for (i = 0; i < 2; i++)
|
||||
if (vec_bll_result[i] != vec_bll_expected[i])
|
||||
#ifdef DEBUG
|
||||
printf("ERROR vec_mergee(): vec_bll_result[%d] = %lld, vec_bll_expected[%d] = %lld\n",
|
||||
i, vec_ull_result[i],
|
||||
i, vec_ull_expected[i]);
|
||||
#else
|
||||
abort();
|
||||
#endif
|
||||
|
||||
vec_f_arg1 = (vector float){100.0, 101.1, 102.2, 103.3};
|
||||
vec_f_arg2 = (vector float){200.0, 201.1, 202.2, 203.3};
|
||||
|
||||
vec_f_result = vec_mergee (vec_f_arg1, vec_f_arg2);
|
||||
|
||||
vec_f_expected = (vector float){100.0, 200.0, 102.2, 202.2};
|
||||
|
||||
for (i = 0; i < 4; i++)
|
||||
if (vec_f_result[i] != vec_f_expected[i])
|
||||
#ifdef DEBUG
|
||||
printf("ERROR vec_mergee(): vec_f_result[%d] = %f, vec_f_expected[%d] = %f\n",
|
||||
i, vec_f_result[i], i, vec_f_expected[i]);
|
||||
#else
|
||||
abort();
|
||||
#endif
|
||||
|
||||
vec_d_arg1 = (vector double){300.0, 301.1};
|
||||
vec_d_arg2 = (vector double){400.0, 401.1};
|
||||
|
||||
vec_d_result = vec_mergee (vec_d_arg1, vec_d_arg2);
|
||||
|
||||
vec_d_expected = (vector double){300.0, 400.0};
|
||||
|
||||
for (i = 0; i < 2; i++)
|
||||
if (vec_d_result[i] != vec_d_expected[i])
|
||||
#ifdef DEBUG
|
||||
printf("ERROR vec_mergee(): vec_d_result[%d] = %f, vec_d_expected[%d] = %f\n",
|
||||
i, vec_d_result[i], i, vec_d_expected[i]);
|
||||
#else
|
||||
abort();
|
||||
#endif
|
||||
}
|
||||
Loading…
Reference in New Issue