mirror of git://gcc.gnu.org/git/gcc.git
re PR target/85683 (GCC 8 stopped using RMW (Read Modify Write) instructions on x86[_64])
PR target/85683
* config/i386/i386.md: Add peepholes for mem {+,-,&,|,^}= x; mem != 0
after cmpelim optimization.
* gcc.target/i386/pr49095.c: Add -masm=att to dg-options. Add
scan-assembler-times checking that except for [fh]*xor other functions
don't use any load instructions.
From-SVN: r260045
This commit is contained in:
Jakub Jelinek
Jakub Jelinek
parent
41c3db9f28
commit
1eac383063
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@ -1,3 +1,9 @@
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2018-05-08 Jakub Jelinek <jakub@redhat.com>
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PR target/85683
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* config/i386/i386.md: Add peepholes for mem {+,-,&,|,^}= x; mem != 0
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after cmpelim optimization.
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2018-05-08 Olga Makhotina <olga.makhotina@intel.com>
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2018-05-08 Olga Makhotina <olga.makhotina@intel.com>
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* config.gcc: Support "goldmont".
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* config.gcc: Support "goldmont".
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@ -19286,6 +19286,37 @@
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const0_rtx);
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const0_rtx);
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})
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})
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;; Likewise for cmpelim optimized pattern.
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(define_peephole2
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[(set (match_operand:SWI 0 "register_operand")
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(match_operand:SWI 1 "memory_operand"))
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(parallel [(set (reg FLAGS_REG)
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(compare (match_operator:SWI 3 "plusminuslogic_operator"
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[(match_dup 0)
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(match_operand:SWI 2 "<nonmemory_operand>")])
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(const_int 0)))
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(set (match_dup 0) (match_dup 3))])
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(set (match_dup 1) (match_dup 0))]
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"(TARGET_READ_MODIFY_WRITE || optimize_insn_for_size_p ())
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&& peep2_reg_dead_p (3, operands[0])
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&& !reg_overlap_mentioned_p (operands[0], operands[1])
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&& !reg_overlap_mentioned_p (operands[0], operands[2])
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&& ix86_match_ccmode (peep2_next_insn (1),
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(GET_CODE (operands[3]) == PLUS
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|| GET_CODE (operands[3]) == MINUS)
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? CCGOCmode : CCNOmode)"
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[(parallel [(set (match_dup 4) (match_dup 6))
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(set (match_dup 1) (match_dup 5))])]
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{
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operands[4] = SET_DEST (XVECEXP (PATTERN (peep2_next_insn (1)), 0, 0));
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operands[5]
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= gen_rtx_fmt_ee (GET_CODE (operands[3]), GET_MODE (operands[3]),
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copy_rtx (operands[1]), operands[2]);
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operands[6]
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= gen_rtx_COMPARE (GET_MODE (operands[4]), copy_rtx (operands[5]),
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const0_rtx);
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})
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;; Likewise for instances where we have a lea pattern.
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;; Likewise for instances where we have a lea pattern.
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(define_peephole2
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(define_peephole2
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[(set (match_operand:SWI 0 "register_operand")
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[(set (match_operand:SWI 0 "register_operand")
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@ -19349,6 +19380,34 @@
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const0_rtx);
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const0_rtx);
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})
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})
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;; Likewise for cmpelim optimized pattern.
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(define_peephole2
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[(parallel [(set (reg FLAGS_REG)
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(compare (match_operator:SWI 2 "plusminuslogic_operator"
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[(match_operand:SWI 0 "register_operand")
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(match_operand:SWI 1 "memory_operand")])
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(const_int 0)))
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(set (match_dup 0) (match_dup 2))])
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(set (match_dup 1) (match_dup 0))]
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"(TARGET_READ_MODIFY_WRITE || optimize_insn_for_size_p ())
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&& peep2_reg_dead_p (2, operands[0])
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&& !reg_overlap_mentioned_p (operands[0], operands[1])
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&& ix86_match_ccmode (peep2_next_insn (0),
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(GET_CODE (operands[2]) == PLUS
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|| GET_CODE (operands[2]) == MINUS)
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? CCGOCmode : CCNOmode)"
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[(parallel [(set (match_dup 3) (match_dup 5))
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(set (match_dup 1) (match_dup 4))])]
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{
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operands[3] = SET_DEST (XVECEXP (PATTERN (peep2_next_insn (0)), 0, 0));
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operands[4]
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= gen_rtx_fmt_ee (GET_CODE (operands[2]), GET_MODE (operands[2]),
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copy_rtx (operands[1]), operands[0]);
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operands[5]
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= gen_rtx_COMPARE (GET_MODE (operands[3]), copy_rtx (operands[4]),
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const0_rtx);
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})
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(define_peephole2
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(define_peephole2
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[(set (match_operand:SWI12 0 "register_operand")
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[(set (match_operand:SWI12 0 "register_operand")
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(match_operand:SWI12 1 "memory_operand"))
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(match_operand:SWI12 1 "memory_operand"))
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@ -1,3 +1,10 @@
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2018-05-08 Jakub Jelinek <jakub@redhat.com>
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PR target/85683
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* gcc.target/i386/pr49095.c: Add -masm=att to dg-options. Add
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scan-assembler-times checking that except for [fh]*xor other functions
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don't use any load instructions.
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2018-05-08 Olga Makhotina <olga.makhotina@intel.com>
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2018-05-08 Olga Makhotina <olga.makhotina@intel.com>
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* gcc.target/i386/builtin_target.c: Test goldmont.
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* gcc.target/i386/builtin_target.c: Test goldmont.
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@ -1,6 +1,6 @@
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/* PR rtl-optimization/49095 */
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/* PR rtl-optimization/49095 */
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/* { dg-do compile } */
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/* { dg-do compile } */
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/* { dg-options "-Os -fno-shrink-wrap" } */
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/* { dg-options "-Os -fno-shrink-wrap -masm=att" } */
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/* { dg-additional-options "-mregparm=2" { target ia32 } } */
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/* { dg-additional-options "-mregparm=2" { target ia32 } } */
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void foo (void *);
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void foo (void *);
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@ -71,3 +71,6 @@ G (int)
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G (long)
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G (long)
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/* { dg-final { scan-assembler-not "test\[lq\]" } } */
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/* { dg-final { scan-assembler-not "test\[lq\]" } } */
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/* The {f,h}{char,short,int,long}xor functions aren't optimized into
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a RMW instruction, so need load, modify and store. FIXME eventually. */
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/* { dg-final { scan-assembler-times "\\), %" 8 } } */
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