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re PR middle-end/70680 (OpenMP SIMD linear variable privatized too eagerly) 

[gcc]
2016-04-12  Michael Meissner  <meissner@linux.vnet.ibm.com>

	PR target/70680
	* config/rs6000/rs6000.md (ieee_128bit_vsx_neg<mode>2_internal):
	Do not use "=" constraint on an input constraint.
	(ieee_128bit_vsx_abs<mode>2_internal): Likewise.
	(ieee_128bit_vsx_nabs<mode>2_internal): Likewise.
	(ieee_128bit_vsx_nabs<mode>2): Correct splitter so that it
	generates (neg (abs ...)) instead of (abs ...).

[gcc/testsuite]
2016-04-12  Michael Meissner  <meissner@linux.vnet.ibm.com>

	PR target/70680
	* gcc.target/powerpc/pr70640.c: New test.

From-SVN: r234910
This commit is contained in:
Michael Meissner 2016-04-12 19:25:56 +00:00 committed by Michael Meissner
parent 2b2f52bccf
commit 20b9851c46
4 changed files with 30 additions and 4 deletions
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10
gcc/ChangeLog
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@ -1,3 +1,13 @@
2016-04-12 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/70680
* config/rs6000/rs6000.md (ieee_128bit_vsx_neg<mode>2_internal):
Do not use "=" constraint on an input constraint.
(ieee_128bit_vsx_abs<mode>2_internal): Likewise.
(ieee_128bit_vsx_nabs<mode>2_internal): Likewise.
(ieee_128bit_vsx_nabs<mode>2): Correct splitter so that it
generates (neg (abs ...)) instead of (abs ...).
2016-04-12 Jakub Jelinek <jakub@redhat.com> 2016-04-12 Jakub Jelinek <jakub@redhat.com>
PR rtl-optimization/70596 PR rtl-optimization/70596

8
gcc/config/rs6000/rs6000.md
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@ -7261,7 +7261,7 @@
(define_insn "*ieee_128bit_vsx_neg<mode>2_internal" (define_insn "*ieee_128bit_vsx_neg<mode>2_internal"
[(set (match_operand:IEEE128 0 "register_operand" "=wa") [(set (match_operand:IEEE128 0 "register_operand" "=wa")
(neg:IEEE128 (match_operand:IEEE128 1 "register_operand" "wa"))) (neg:IEEE128 (match_operand:IEEE128 1 "register_operand" "wa")))
(use (match_operand:V16QI 2 "register_operand" "=v"))] (use (match_operand:V16QI 2 "register_operand" "v"))]
"TARGET_FLOAT128 && !TARGET_FLOAT128_HW" "TARGET_FLOAT128 && !TARGET_FLOAT128_HW"
"xxlxor %x0,%x1,%x2" "xxlxor %x0,%x1,%x2"
[(set_attr "type" "vecsimple")]) [(set_attr "type" "vecsimple")])
@ -7290,7 +7290,7 @@
(define_insn "*ieee_128bit_vsx_abs<mode>2_internal" (define_insn "*ieee_128bit_vsx_abs<mode>2_internal"
[(set (match_operand:IEEE128 0 "register_operand" "=wa") [(set (match_operand:IEEE128 0 "register_operand" "=wa")
(abs:IEEE128 (match_operand:IEEE128 1 "register_operand" "wa"))) (abs:IEEE128 (match_operand:IEEE128 1 "register_operand" "wa")))
(use (match_operand:V16QI 2 "register_operand" "=v"))] (use (match_operand:V16QI 2 "register_operand" "v"))]
"TARGET_FLOAT128 && !TARGET_FLOAT128_HW" "TARGET_FLOAT128 && !TARGET_FLOAT128_HW"
"xxlandc %x0,%x1,%x2" "xxlandc %x0,%x1,%x2"
[(set_attr "type" "vecsimple")]) [(set_attr "type" "vecsimple")])
@ -7306,7 +7306,7 @@
"#" "#"
"&& 1" "&& 1"
[(parallel [(set (match_dup 0) [(parallel [(set (match_dup 0)
(abs:IEEE128 (match_dup 1))) (neg:IEEE128 (abs:IEEE128 (match_dup 1))))
(use (match_dup 2))])] (use (match_dup 2))])]
{ {
if (GET_CODE (operands[2]) == SCRATCH) if (GET_CODE (operands[2]) == SCRATCH)
@ -7323,7 +7323,7 @@
(neg:IEEE128 (neg:IEEE128
(abs:IEEE128 (abs:IEEE128
(match_operand:IEEE128 1 "register_operand" "wa")))) (match_operand:IEEE128 1 "register_operand" "wa"))))
(use (match_operand:V16QI 2 "register_operand" "=v"))] (use (match_operand:V16QI 2 "register_operand" "v"))]
"TARGET_FLOAT128 && !TARGET_FLOAT128_HW" "TARGET_FLOAT128 && !TARGET_FLOAT128_HW"
"xxlor %x0,%x1,%x2" "xxlor %x0,%x1,%x2"
[(set_attr "type" "vecsimple")]) [(set_attr "type" "vecsimple")])

5
gcc/testsuite/ChangeLog
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@ -1,3 +1,8 @@
2016-04-12 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/70680
* gcc.target/powerpc/pr70640.c: New test.
2016-04-12 Paolo Carlini <paolo.carlini@oracle.com> 2016-04-12 Paolo Carlini <paolo.carlini@oracle.com>
PR c++/68722 PR c++/68722

11
gcc/testsuite/gcc.target/powerpc/pr70640.c Normal file
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@ -0,0 +1,11 @@
/* { dg-do compile { target { powerpc*-*-linux* } } } */
/* { dg-require-effective-target powerpc_float128_sw_ok } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
/* { dg-options "-O2 -mcpu=power8 -mfloat128" } */
__float128 foo (__float128 a) { return -a; }
/* { dg-final { scan-assembler "xxlorc" } } */
/* { dg-final { scan-assembler "xxlxor" } } */
/* { dg-final { scan-assembler "vslb" } } */
/* { dg-final { scan-assembler "vsldoi" } } */