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[ARC] Update movhi and movdi patterns. 

Allow signed 6-bit short immediates into st[d] instructions.

2017-10-19  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/arc.c (arc_split_move): Allow signed 6-bit constants
	as source of std instructions.
	* config/arc/arc.md (movsi_insn): Update pattern predicate to
	allow 6-bit constants as source for store instructions.
	(movdi_insn): Update instruction pattern to allow 6-bit constants
	as source for store instructions.

testsuite/
2017-10-19  Claudiu Zissulescu  <claziss@synopsys.com>

	* gcc.target/arc/store-merge-1.c: New test.
	* gcc.target/arc/add_n-combine.c: Update test.

From-SVN: r259762
This commit is contained in:
Claudiu Zissulescu 2018-04-30 15:15:35 +02:00 committed by Claudiu Zissulescu
parent e2df7e6df4
commit 2295aa7522
6 changed files with 47 additions and 14 deletions
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9
gcc/ChangeLog
View File

@ -1,3 +1,12 @@
2018-04-30 Claudiu Zissulescu <claziss@synopsys.com>
* config/arc/arc.c (arc_split_move): Allow signed 6-bit constants
as source of std instructions.
* config/arc/arc.md (movsi_insn): Update pattern predicate to
allow 6-bit constants as source for store instructions.
(movdi_insn): Update instruction pattern to allow 6-bit constants
as source for store instructions.
2018-04-30 Jonathan Wakely <jwakely@redhat.com> 2018-04-30 Jonathan Wakely <jwakely@redhat.com>
* doc/invoke.texi (-fdebug-types-section): Fix grammar. * doc/invoke.texi (-fdebug-types-section): Fix grammar.

3
gcc/config/arc/arc.c
View File

@ -9651,7 +9651,8 @@ arc_split_move (rtx *operands)
if (TARGET_LL64 if (TARGET_LL64
&& ((memory_operand (operands[0], mode) && ((memory_operand (operands[0], mode)
&& even_register_operand (operands[1], mode)) && (even_register_operand (operands[1], mode)
|| satisfies_constraint_Cm3 (operands[1])))
|| (memory_operand (operands[1], mode) || (memory_operand (operands[1], mode)
&& even_register_operand (operands[0], mode)))) && even_register_operand (operands[0], mode))))
{ {

25
gcc/config/arc/arc.md
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@ -724,7 +724,9 @@
/* Don't use a LIMM that we could load with a single insn - we loose /* Don't use a LIMM that we could load with a single insn - we loose
delay-slot filling opportunities. */ delay-slot filling opportunities. */
&& !satisfies_constraint_I (operands[1]) && !satisfies_constraint_I (operands[1])
&& satisfies_constraint_Usc (operands[0]))" && satisfies_constraint_Usc (operands[0]))
|| (satisfies_constraint_Cm3 (operands[1])
&& memory_operand (operands[0], SImode))"
"@ "@
mov%? %0,%1%& ;0 mov%? %0,%1%& ;0
mov%? %0,%1%& ;1 mov%? %0,%1%& ;1
@ -1221,10 +1223,12 @@
") ")
(define_insn_and_split "*movdi_insn" (define_insn_and_split "*movdi_insn"
[(set (match_operand:DI 0 "move_dest_operand" "=w, w,r,m") [(set (match_operand:DI 0 "move_dest_operand" "=w, w,r, m")
(match_operand:DI 1 "move_double_src_operand" "c,Hi,m,c"))] (match_operand:DI 1 "move_double_src_operand" "c,Hi,m,cCm3"))]
"register_operand (operands[0], DImode) "register_operand (operands[0], DImode)
|| register_operand (operands[1], DImode)" || register_operand (operands[1], DImode)
|| (satisfies_constraint_Cm3 (operands[1])
&& memory_operand (operands[0], DImode))"
"* "*
{ {
switch (which_alternative) switch (which_alternative)
@ -1234,19 +1238,16 @@
case 2: case 2:
if (TARGET_LL64 if (TARGET_LL64
&& ((even_register_operand (operands[0], DImode) && memory_operand (operands[1], DImode)
&& memory_operand (operands[1], DImode)) && even_register_operand (operands[0], DImode))
|| (memory_operand (operands[0], DImode)
&& even_register_operand (operands[1], DImode))))
return \"ldd%U1%V1 %0,%1%&\"; return \"ldd%U1%V1 %0,%1%&\";
return \"#\"; return \"#\";
case 3: case 3:
if (TARGET_LL64 if (TARGET_LL64
&& ((even_register_operand (operands[0], DImode) && memory_operand (operands[0], DImode)
&& memory_operand (operands[1], DImode)) && (even_register_operand (operands[1], DImode)
|| (memory_operand (operands[0], DImode) || satisfies_constraint_Cm3 (operands[1])))
&& even_register_operand (operands[1], DImode))))
return \"std%U0%V0 %1,%0\"; return \"std%U0%V0 %1,%0\";
return \"#\"; return \"#\";
} }

5
gcc/testsuite/ChangeLog
View File

@ -1,3 +1,8 @@
2018-04-30 Claudiu Zissulescu <claziss@synopsys.com>
* gcc.target/arc/store-merge-1.c: New test.
* gcc.target/arc/add_n-combine.c: Update test.
2018-04-30 Andrew Sadek <andrew.sadek.se@gmail.com> 2018-04-30 Andrew Sadek <andrew.sadek.se@gmail.com>
Microblaze Target: PIC data text relative Microblaze Target: PIC data text relative

2
gcc/testsuite/gcc.target/arc/add_n-combine.c
View File

@ -45,4 +45,4 @@ void f() {
a(at3.bn[bu]); a(at3.bn[bu]);
} }
/* { dg-final { scan-rtl-dump-times "\\*add_n" 3 "combine" } } */ /* { dg-final { scan-rtl-dump-times "\\*add_n" 2 "combine" } } */

17
gcc/testsuite/gcc.target/arc/store-merge-1.c Normal file
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@ -0,0 +1,17 @@
/* { dg-do compile } */
/* { dg-options "-O3" } */
/* This tests checks if we use st w6,[reg] format. */
typedef struct {
unsigned long __val[2];
} sigset_t;
int sigemptyset2 (sigset_t *set)
{
set->__val[0] = 0;
set->__val[1] = 0;
return 0;
}
/* { dg-final { scan-assembler-times "st 0,\\\[r" 2 } } */