mirror of git://gcc.gnu.org/git/gcc.git
AArch64: Implement widen_[us]sum using [US]ADDW[TB] for SVE2 [PR122069]
SVE2 adds [US]ADDW[TB] which we can use when we have to do a single step
widening addition. This is useful for instance when the value to be widened
does not come from a load. For example for
int foo2_int(unsigned short *x, unsigned short * restrict y) {
int sum = 0;
for (int i = 0; i < 8000; i++)
{
x[i] = x[i] + y[i];
sum += x[i];
}
return sum;
}
we used to generate
.L6:
ld1h z1.h, p7/z, [x0, x2, lsl 1]
ld1h z29.h, p7/z, [x1, x2, lsl 1]
add z29.h, z29.h, z1.h
punpklo p6.h, p7.b
uunpklo z0.s, z29.h
add z31.s, p6/m, z31.s, z0.s
punpkhi p6.h, p7.b
uunpkhi z30.s, z29.h
add z31.s, p6/m, z31.s, z30.s
st1h z29.h, p7, [x0, x2, lsl 1]
add x2, x2, x4
whilelo p7.h, w2, w3
b.any .L6
ptrue p7.b, all
uaddv d31, p7, z31.s
but with +sve2
.L12:
ld1h z30.h, p7/z, [x0, x2, lsl 1]
ld1h z29.h, p7/z, [x1, x2, lsl 1]
add z30.h, z30.h, z29.h
uaddwb z31.s, z31.s, z30.h
uaddwt z31.s, z31.s, z30.h
st1h z30.h, p7, [x0, x2, lsl 1]
mov x3, x2
inch x2
cmp w2, w4
bls .L12
inch x3
uaddv d31, p7, z31.s
gcc/ChangeLog:
PR middle-end/122069
* config/aarch64/aarch64-sve2.md: (widen_ssum<mode><Vnarrow>3): New.
(widen_usum<mode><Vnarrow>3): New.
* config/aarch64/iterators.md (Vnarrow): New, to match VNARROW.
gcc/testsuite/ChangeLog:
PR middle-end/122069
* gcc.target/aarch64/sve2/pr122069_1.c: New test.
* gcc.target/aarch64/sve2/pr122069_2.c: New test.
This commit is contained in:
Tamar Christina
parent
2f719014bf
commit
25c8a8d431
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@ -2377,6 +2377,36 @@
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[(set_attr "sve_type" "sve_int_general")]
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)
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;; Define single step widening for widen_ssum using SADDWB and SADDWT
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(define_expand "widen_ssum<mode><Vnarrow>3"
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[(set (match_operand:SVE_FULL_HSDI 0 "register_operand")
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(unspec:SVE_FULL_HSDI
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[(match_operand:SVE_FULL_HSDI 2 "register_operand")
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(match_operand:<VNARROW> 1 "register_operand")]
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UNSPEC_SADDWB))
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(set (match_dup 0)
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(unspec:SVE_FULL_HSDI
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[(match_dup 0)
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(match_dup 1)]
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UNSPEC_SADDWT))]
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"TARGET_SVE2"
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)
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;; Define single step widening for widen_usum using UADDWB and UADDWT
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(define_expand "widen_usum<mode><Vnarrow>3"
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[(set (match_operand:SVE_FULL_HSDI 0 "register_operand" "=w")
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(unspec:SVE_FULL_HSDI
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[(match_operand:SVE_FULL_HSDI 2 "register_operand" "w")
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(match_operand:<VNARROW> 1 "register_operand" "w")]
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UNSPEC_UADDWB))
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(set (match_dup 0)
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(unspec:SVE_FULL_HSDI
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[(match_dup 0)
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(match_dup 1)]
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UNSPEC_UADDWT))]
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"TARGET_SVE2"
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)
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;; -------------------------------------------------------------------------
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;; ---- [INT] Long binary arithmetic
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;; -------------------------------------------------------------------------
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@ -1935,6 +1935,11 @@
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(VNx2DI "VNx4SI") (VNx2DF "VNx4SF")
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(VNx8SI "VNx8HI") (VNx16SI "VNx16QI")
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(VNx8DI "VNx8HI")])
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(define_mode_attr Vnarrow [(VNx8HI "vnx16qi")
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(VNx4SI "vnx8hi") (VNx4SF "vnx8hf")
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(VNx2DI "vnx4si") (VNx2DF "vnx4sf")
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(VNx8SI "vnx8hi") (VNx16SI "vnx16qi")
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(VNx8DI "vnx8hi")])
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;; Suffix mapping Advanced SIMD modes to be expanded as SVE instructions.
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(define_mode_attr sve_di_suf [(VNx16QI "") (VNx8HI "") (VNx4SI "") (VNx2DI "")
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@ -0,0 +1,41 @@
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/* { dg-do compile } */
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/* { dg-options "-O3 -march=armv8-a+sve2 -mautovec-preference=sve-only --param vect-epilogues-nomask=0 -fno-schedule-insns -fno-reorder-blocks -fno-schedule-insns2 -fdump-tree-vect-details" }*/
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/* { dg-final { check-function-bodies "**" "" } } */
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inline char char_abs(char i) {
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return (i < 0 ? -i : i);
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}
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/*
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** foo_int:
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** ...
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** sub z[0-9]+.b, z[0-9]+.b, z[0-9]+.b
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** udot z[0-9]+.s, z[0-9]+.b, z[0-9]+.b
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** ...
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*/
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int foo_int(unsigned char *x, unsigned char * restrict y) {
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int sum = 0;
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for (int i = 0; i < 8000; i++)
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sum += char_abs(x[i] - y[i]);
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return sum;
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}
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/*
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** foo2_int:
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** ...
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** add z[0-9]+.h, z[0-9]+.h, z[0-9]+.h
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** uaddwb z[0-9]+.s, z[0-9]+.s, z[0-9]+.h
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** uaddwt z[0-9]+.s, z[0-9]+.s, z[0-9]+.h
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** ...
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*/
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int foo2_int(unsigned short *x, unsigned short * restrict y) {
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int sum = 0;
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for (int i = 0; i < 8000; i++)
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{
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x[i] = x[i] + y[i];
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sum += x[i];
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}
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return sum;
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}
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/* { dg-final { scan-tree-dump-times "LOOP VECTORIZED" 2 "vect" } } */
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@ -0,0 +1,81 @@
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/* { dg-do run } */
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/* { dg-require-effective-target aarch64_sve2_hw } */
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/* { dg-options "-O3 -march=armv8-a+sve2 -mautovec-preference=sve-only -fdump-tree-vect-details" }*/
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inline char char_abs(char i) {
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return (i < 0 ? -i : i);
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}
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__attribute__((noipa))
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int foo_int(unsigned char *x, unsigned char * restrict y) {
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int sum = 0;
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for (int i = 0; i < 100; i++)
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sum += char_abs(x[i] - y[i]);
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return sum;
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}
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__attribute__((noipa))
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int foo2_int(unsigned short *x, unsigned short * restrict y,
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unsigned short * restrict z) {
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int sum = 0;
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for (int i = 0; i < 100; i++)
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{
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z[i] = x[i] + y[i];
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sum += z[i];
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}
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return sum;
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}
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__attribute__((noipa))
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int foo_int2(unsigned char *x, unsigned char * restrict y) {
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int sum = 0;
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#pragma GCC novector
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for (int i = 0; i < 100; i++)
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sum += char_abs(x[i] - y[i]);
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return sum;
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}
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__attribute__((noipa))
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int foo2_int2(unsigned short *x, unsigned short * restrict y,
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unsigned short * restrict z) {
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int sum = 0;
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#pragma GCC novector
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for (int i = 0; i < 100; i++)
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{
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z[i] = x[i] + y[i];
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sum += z[i];
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}
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return sum;
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}
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int main ()
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{
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unsigned short a[100];
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unsigned short b[100];
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unsigned short r1[100];
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unsigned short r2[100];
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unsigned char c[100];
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unsigned char d[100];
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#pragma GCC novector
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for (int i = 0; i < 100; i++)
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{
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a[i] = c[i] = i;
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b[i] = d[i] = 100 - i;
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}
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if (foo_int (c, d) != foo_int2 (c, d))
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__builtin_abort();
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if (foo2_int (a, b, r1) != foo2_int2 (a, b, r2))
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__builtin_abort();
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#pragma GCC novector
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for (int i = 0; i < 100; i++)
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if (r1[i] != r2[i])
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__builtin_abort ();
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return 0;
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}
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/* { dg-final { scan-tree-dump-times "LOOP VECTORIZED" 2 "vect" } } */
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