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[AArch64] Use SUBS for parallel subtraction and comparison with immediate 

* config/aarch64/aarch64.md (sub<mode>3_compare1_imm): New define_insn.
	(peephole2): New peephole2 to emit the above.
	* config/aarch64/predicates.md (aarch64_sub_immediate): New predicate.

	* gcc.target/aarch64/subs_compare_2.c: New test.

From-SVN: r248870
This commit is contained in:
Kyrylo Tkachov 2017-06-05 08:49:59 +00:00 committed by Kyrylo Tkachov
parent e49d8b68a2
commit 279dc4b464
5 changed files with 60 additions and 0 deletions
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6
gcc/ChangeLog
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@ -1,3 +1,9 @@
2017-06-05 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/aarch64.md (sub<mode>3_compare1_imm): New define_insn.
(peephole2): New peephole2 to emit the above.
* config/aarch64/predicates.md (aarch64_sub_immediate): New predicate.
2017-06-05 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/aarch64.c (define_peephole2 above

31
gcc/config/aarch64/aarch64.md
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@ -2234,6 +2234,19 @@
[(set_attr "type" "alus_sreg")]
)
(define_insn "sub<mode>3_compare1_imm"
[(set (reg:CC CC_REGNUM)
(compare:CC
(match_operand:GPI 1 "register_operand" "r")
(match_operand:GPI 3 "const_int_operand" "n")))
(set (match_operand:GPI 0 "register_operand" "=r")
(plus:GPI (match_dup 1)
(match_operand:GPI 2 "aarch64_sub_immediate" "J")))]
"INTVAL (operands[3]) == -INTVAL (operands[2])"
"subs\\t%<w>0, %<w>1, #%n2"
[(set_attr "type" "alus_sreg")]
)
(define_peephole2
[(set (match_operand:GPI 0 "register_operand")
(minus:GPI (match_operand:GPI 1 "aarch64_reg_or_zero")
@ -2252,6 +2265,24 @@
}
)
(define_peephole2
[(set (match_operand:GPI 0 "register_operand")
(plus:GPI (match_operand:GPI 1 "register_operand")
(match_operand:GPI 2 "aarch64_sub_immediate")))
(set (reg:CC CC_REGNUM)
(compare:CC
(match_dup 1)
(match_operand:GPI 3 "const_int_operand")))]
"!reg_overlap_mentioned_p (operands[0], operands[1])
&& INTVAL (operands[3]) == -INTVAL (operands[2])"
[(const_int 0)]
{
emit_insn (gen_sub<mode>3_compare1_imm (operands[0], operands[1],
operands[2], operands[3]));
DONE;
}
)
(define_insn "*sub_<shift>_<mode>"
[(set (match_operand:GPI 0 "register_operand" "=r")
(minus:GPI (match_operand:GPI 3 "register_operand" "r")

4
gcc/config/aarch64/predicates.md
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@ -77,6 +77,10 @@
(define_predicate "aarch64_fp_vec_pow2"
(match_test "aarch64_vec_fpconst_pow_of_2 (op) > 0"))
(define_predicate "aarch64_sub_immediate"
(and (match_code "const_int")
(match_test "aarch64_uimm12_shift (-INTVAL (op))")))
(define_predicate "aarch64_plus_immediate"
(and (match_code "const_int")
(ior (match_test "aarch64_uimm12_shift (INTVAL (op))")

4
gcc/testsuite/ChangeLog
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@ -1,3 +1,7 @@
2017-06-05 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* gcc.target/aarch64/subs_compare_2.c: New test.
2017-06-05 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* gcc.target/aarch64/subs_compare_1.c: New test.

15
gcc/testsuite/gcc.target/aarch64/subs_compare_2.c Normal file
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@ -0,0 +1,15 @@
/* { dg-do compile } */
/* { dg-options "-O2" } */
int
foo (int a, int b)
{
int x = a - 4;
if (a < 4)
return x;
else
return 0;
}
/* { dg-final { scan-assembler-times "subs\\tw\[0-9\]+, w\[0-9\]+, #4" 1 } } */
/* { dg-final { scan-assembler-not "cmp\\tw\[0-9\]+, w\[0-9\]+" } } */