mirror of git://gcc.gnu.org/git/gcc.git
re PR target/55073 (Wrong Neon code generation at -O2 caused by -fschedule-insns)
PR target/55073 * arm/neon.md (neon_vtrn<mode>_internal): Split into expand and insn patterns. Re-order insn arguments to tie inputs to outputs. (neon_vzip<mode>_internal): Likewise. (neon_vuzp<mode>_internal): Likewise. * gcc.target/arm/pr55073.C: New test. From-SVN: r193943
This commit is contained in:
Richard Earnshaw
Richard Earnshaw
parent
1d02988986
commit
28131dfe44
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@ -1,3 +1,12 @@
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2012-11-29 Richard Earnshaw <rearnsha@arm.com>
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PR target/55073
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* arm/neon.md (neon_vtrn<mode>_internal): Split into expand
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and insn patterns. Re-order insn arguments to tie inputs to
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outputs.
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(neon_vzip<mode>_internal): Likewise.
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(neon_vuzp<mode>_internal): Likewise.
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2012-11-29 Marc Glisse <marc.glisse@inria.fr>
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PR c++/53094
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@ -4411,16 +4411,29 @@
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[(set_attr "neon_type" "neon_bp_3cycle")]
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)
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(define_insn "neon_vtrn<mode>_internal"
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(define_expand "neon_vtrn<mode>_internal"
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[(parallel
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[(set (match_operand:VDQW 0 "s_register_operand" "")
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(unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "")
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(match_operand:VDQW 2 "s_register_operand" "")]
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UNSPEC_VTRN1))
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(set (match_operand:VDQW 3 "s_register_operand" "")
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(unspec:VDQW [(match_dup 1) (match_dup 2)] UNSPEC_VTRN2))])]
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"TARGET_NEON"
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""
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)
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;; Note: Different operand numbering to handle tied registers correctly.
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(define_insn "*neon_vtrn<mode>_insn"
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[(set (match_operand:VDQW 0 "s_register_operand" "=w")
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(unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0")
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(match_operand:VDQW 2 "s_register_operand" "w")]
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(match_operand:VDQW 3 "s_register_operand" "2")]
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UNSPEC_VTRN1))
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(set (match_operand:VDQW 3 "s_register_operand" "=2")
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(unspec:VDQW [(match_dup 1) (match_dup 2)]
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(set (match_operand:VDQW 2 "s_register_operand" "=w")
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(unspec:VDQW [(match_dup 1) (match_dup 3)]
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UNSPEC_VTRN2))]
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"TARGET_NEON"
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"vtrn.<V_sz_elem>\t%<V_reg>0, %<V_reg>3"
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"vtrn.<V_sz_elem>\t%<V_reg>0, %<V_reg>2"
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[(set (attr "neon_type")
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(if_then_else (match_test "<Is_d_reg>")
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(const_string "neon_bp_simple")
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@ -4438,16 +4451,29 @@
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DONE;
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})
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(define_insn "neon_vzip<mode>_internal"
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(define_expand "neon_vzip<mode>_internal"
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[(parallel
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[(set (match_operand:VDQW 0 "s_register_operand" "")
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(unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "")
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(match_operand:VDQW 2 "s_register_operand" "")]
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UNSPEC_VZIP1))
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(set (match_operand:VDQW 3 "s_register_operand" "")
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(unspec:VDQW [(match_dup 1) (match_dup 2)] UNSPEC_VZIP2))])]
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"TARGET_NEON"
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""
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)
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;; Note: Different operand numbering to handle tied registers correctly.
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(define_insn "*neon_vzip<mode>_insn"
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[(set (match_operand:VDQW 0 "s_register_operand" "=w")
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(unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0")
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(match_operand:VDQW 2 "s_register_operand" "w")]
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(match_operand:VDQW 3 "s_register_operand" "2")]
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UNSPEC_VZIP1))
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(set (match_operand:VDQW 3 "s_register_operand" "=2")
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(unspec:VDQW [(match_dup 1) (match_dup 2)]
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(set (match_operand:VDQW 2 "s_register_operand" "=w")
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(unspec:VDQW [(match_dup 1) (match_dup 3)]
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UNSPEC_VZIP2))]
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"TARGET_NEON"
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"vzip.<V_sz_elem>\t%<V_reg>0, %<V_reg>3"
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"vzip.<V_sz_elem>\t%<V_reg>0, %<V_reg>2"
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[(set (attr "neon_type")
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(if_then_else (match_test "<Is_d_reg>")
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(const_string "neon_bp_simple")
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@ -4465,16 +4491,29 @@
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DONE;
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})
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(define_insn "neon_vuzp<mode>_internal"
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(define_expand "neon_vuzp<mode>_internal"
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[(parallel
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[(set (match_operand:VDQW 0 "s_register_operand" "")
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(unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "")
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(match_operand:VDQW 2 "s_register_operand" "")]
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UNSPEC_VUZP1))
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(set (match_operand:VDQW 3 "s_register_operand" "")
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(unspec:VDQW [(match_dup 1) (match_dup 2)] UNSPEC_VUZP2))])]
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"TARGET_NEON"
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""
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)
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;; Note: Different operand numbering to handle tied registers correctly.
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(define_insn "*neon_vuzp<mode>_insn"
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[(set (match_operand:VDQW 0 "s_register_operand" "=w")
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(unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0")
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(match_operand:VDQW 2 "s_register_operand" "w")]
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(match_operand:VDQW 3 "s_register_operand" "2")]
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UNSPEC_VUZP1))
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(set (match_operand:VDQW 3 "s_register_operand" "=2")
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(unspec:VDQW [(match_dup 1) (match_dup 2)]
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(set (match_operand:VDQW 2 "s_register_operand" "=w")
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(unspec:VDQW [(match_dup 1) (match_dup 3)]
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UNSPEC_VUZP2))]
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"TARGET_NEON"
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"vuzp.<V_sz_elem>\t%<V_reg>0, %<V_reg>3"
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"vuzp.<V_sz_elem>\t%<V_reg>0, %<V_reg>2"
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[(set (attr "neon_type")
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(if_then_else (match_test "<Is_d_reg>")
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(const_string "neon_bp_simple")
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@ -1,3 +1,8 @@
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2012-11-29 Richard Earnshaw <rearnsha@arm.com>
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PR target/55073
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* gcc.target/arm/pr55073.C: New test.
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2012-11-29 Marc Glisse <marc.glisse@inria.fr>
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PR c++/53094
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@ -0,0 +1,74 @@
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/* { dg-do run } */
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/* { dg-require-effective-target arm_neon } */
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/* { dg-options "-O2" } */
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/* { dg-add-options arm_neon } */
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#include <arm_neon.h>
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#include <stdlib.h>
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struct __attribute__((aligned(16))) _v16u8_ {
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uint8x16_t val;
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_v16u8_() { }
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_v16u8_( const uint8x16_t &src) { val = src; }
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_v16u8_( const int16x8_t &src) { val = vreinterpretq_u8_s16(src); }
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_v16u8_( const uint32x4_t &src) { val = vreinterpretq_u8_u32(src); }
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operator uint8x16_t () const { return val; }
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operator int8x16_t () const { return vreinterpretq_s8_u8 (val); }
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operator int16x8_t () const { return vreinterpretq_s16_u8(val); }
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operator uint32x4_t () const { return vreinterpretq_u32_u8(val); }
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operator int32x4_t () const { return vreinterpretq_s32_u8(val); }
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};
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typedef struct _v16u8_ v16u8;
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typedef const v16u8 cv16u8;
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typedef v16u8 v16i8;
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typedef v16u8 v8i16;
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typedef v16u8 v4u32;
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inline v16u8 __attribute__((always_inline)) mergelo( const v16u8 & s, const v16u8 & t )
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{
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uint8x8x2_t r = vzip_u8( vget_low_u8(s), vget_low_u8(t) );
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return vcombine_u8( r.val[0], r.val[1] );
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}
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inline v8i16 __attribute__((always_inline)) unpacklo(const v16i8 & s)
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{
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return vmovl_s8( vget_low_s8( s ) );
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}
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const uint32_t __attribute__((aligned(16))) _InA [4] = { 0xFF020001, 0xFF020001, 0xFF000101, 0xFF000101 } ;
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const uint32_t __attribute__((aligned(16))) _InB [4] = { 0xFF050002, 0xFF050002, 0xFF000303, 0xFF000203 } ;
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__attribute__((noinline)) v16i8 test_func(void)
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{
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v16u8 A = vld1q_u8( (uint8_t*) _InA );
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v16u8 B = vld1q_u8( (uint8_t*) _InB );
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v8i16 r = vdupq_n_s16(2);
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v16u8 _0 = mergelo( A, B );
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v16u8 _1 = mergelo( B, A );
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v16u8 _2 = mergelo( _0, _1 );
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v16u8 _3 = mergelo( _1, _0 );
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v8i16 _4 = vsubq_s16( unpacklo( _2 ), r );
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v8i16 _5 = vsubq_s16( unpacklo( _3 ), r );
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v8i16 ret = vaddq_s16( _4, _5 );
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return ( ret );
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}
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int main (int argc, char **argv)
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{
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v16u8 val = test_func();
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if (vgetq_lane_u32( val, 0 ) != 0xffffffff
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|| vgetq_lane_u32( val, 1 ) != 0xffffffff
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|| vgetq_lane_u32( val, 2 ) != 0xfffcfffc
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|| vgetq_lane_u32( val, 3 ) != 0xfffcfffc)
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abort ();
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exit (0);
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}
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