mirror of git://gcc.gnu.org/git/gcc.git
re PR target/50751 (SH Target: Displacement addressing does not work for QImode and HImode)
PR target/50751 * config/sh/sh.md (*extendqisi2_compact_reg, *extendhisi2_compact_reg): Use arith_reg_operand predicate instead of register_operand. * config/sh/predicates.md (movsrc_no_disp_mem_operand): Accept only mem, simplify. From-SVN: r190257
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@ -1,3 +1,11 @@
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2012-08-09 Oleg Endo <olegendo@gcc.gnu.org>
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PR target/50751
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* config/sh/sh.md (*extendqisi2_compact_reg, *extendhisi2_compact_reg):
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Use arith_reg_operand predicate instead of register_operand.
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* config/sh/predicates.md (movsrc_no_disp_mem_operand): Accept
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only mem, simplify.
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2012-08-09 Uros Bizjak <ubizjak@gmail.com>
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2012-08-09 Uros Bizjak <ubizjak@gmail.com>
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* config/alpha/alpha.c (alpha_pad_noreturn): Rename to ...
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* config/alpha/alpha.c (alpha_pad_noreturn): Rename to ...
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@ -428,28 +428,12 @@
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return general_operand (op, mode);
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return general_operand (op, mode);
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})
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})
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;; Same as movsrc_operand, but rejects displacement addressing.
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;; Returns 1 if OP is a MEM that does not use displacement addressing.
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(define_predicate "movsrc_no_disp_mem_operand"
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(define_predicate "movsrc_no_disp_mem_operand"
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(match_code "subreg,reg,const_int,const_double,mem,symbol_ref,label_ref,const,const_vector")
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(match_code "mem")
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{
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{
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if (!general_movsrc_operand (op, mode))
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return general_movsrc_operand (op, mode) && satisfies_constraint_Snd (op);
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return 0;
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if ((mode == QImode || mode == HImode)
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&& mode == GET_MODE (op)
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&& (MEM_P (op)
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|| (GET_CODE (op) == SUBREG && MEM_P (SUBREG_REG (op)))))
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{
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rtx x = XEXP ((MEM_P (op) ? op : SUBREG_REG (op)), 0);
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if (GET_CODE (x) == PLUS
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&& REG_P (XEXP (x, 0))
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&& CONST_INT_P (XEXP (x, 1)))
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return 0;
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}
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return 1;
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})
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})
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;; Returns 1 if OP can be a destination of a move. Same as
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;; Returns 1 if OP can be a destination of a move. Same as
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@ -4819,14 +4819,14 @@ label:
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(define_insn "*extendqisi2_compact_reg"
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(define_insn "*extendqisi2_compact_reg"
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[(set (match_operand:SI 0 "arith_reg_dest" "=r")
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[(set (match_operand:SI 0 "arith_reg_dest" "=r")
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(sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
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(sign_extend:SI (match_operand:QI 1 "arith_reg_operand" "r")))]
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"TARGET_SH1"
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"TARGET_SH1"
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"exts.b %1,%0"
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"exts.b %1,%0"
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[(set_attr "type" "arith")])
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[(set_attr "type" "arith")])
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(define_insn "*extendhisi2_compact_reg"
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(define_insn "*extendhisi2_compact_reg"
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[(set (match_operand:SI 0 "arith_reg_dest" "=r")
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[(set (match_operand:SI 0 "arith_reg_dest" "=r")
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(sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
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(sign_extend:SI (match_operand:HI 1 "arith_reg_operand" "r")))]
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"TARGET_SH1"
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"TARGET_SH1"
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"exts.w %1,%0"
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"exts.w %1,%0"
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[(set_attr "type" "arith")])
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[(set_attr "type" "arith")])
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