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re PR target/50751 (SH Target: Displacement addressing does not work for QImode and HImode) 

PR target/50751
	* config/sh/sh.md (*extendqisi2_compact_reg, *extendhisi2_compact_reg):
	Use arith_reg_operand predicate instead of register_operand.
	* config/sh/predicates.md (movsrc_no_disp_mem_operand): Accept
	only mem, simplify.

From-SVN: r190257
This commit is contained in:
Oleg Endo 2012-08-09 15:51:20 +00:00
parent 3eda5123a4
commit 284c32cfd8
3 changed files with 13 additions and 21 deletions
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8
gcc/ChangeLog
View File

@ -1,3 +1,11 @@
2012-08-09 Oleg Endo <olegendo@gcc.gnu.org>
PR target/50751
* config/sh/sh.md (*extendqisi2_compact_reg, *extendhisi2_compact_reg):
Use arith_reg_operand predicate instead of register_operand.
* config/sh/predicates.md (movsrc_no_disp_mem_operand): Accept
only mem, simplify.
2012-08-09 Uros Bizjak <ubizjak@gmail.com>
* config/alpha/alpha.c (alpha_pad_noreturn): Rename to ...

22
gcc/config/sh/predicates.md
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@ -428,28 +428,12 @@
return general_operand (op, mode);
})
;; Same as movsrc_operand, but rejects displacement addressing.
;; Returns 1 if OP is a MEM that does not use displacement addressing.
(define_predicate "movsrc_no_disp_mem_operand"
(match_code "subreg,reg,const_int,const_double,mem,symbol_ref,label_ref,const,const_vector")
(match_code "mem")
{
if (!general_movsrc_operand (op, mode))
return 0;
if ((mode == QImode || mode == HImode)
&& mode == GET_MODE (op)
&& (MEM_P (op)
|| (GET_CODE (op) == SUBREG && MEM_P (SUBREG_REG (op)))))
{
rtx x = XEXP ((MEM_P (op) ? op : SUBREG_REG (op)), 0);
if (GET_CODE (x) == PLUS
&& REG_P (XEXP (x, 0))
&& CONST_INT_P (XEXP (x, 1)))
return 0;
}
return 1;
return general_movsrc_operand (op, mode) && satisfies_constraint_Snd (op);
})
;; Returns 1 if OP can be a destination of a move. Same as

4
gcc/config/sh/sh.md
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@ -4819,14 +4819,14 @@ label:
(define_insn "*extendqisi2_compact_reg"
[(set (match_operand:SI 0 "arith_reg_dest" "=r")
(sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
(sign_extend:SI (match_operand:QI 1 "arith_reg_operand" "r")))]
"TARGET_SH1"
"exts.b %1,%0"
[(set_attr "type" "arith")])
(define_insn "*extendhisi2_compact_reg"
[(set (match_operand:SI 0 "arith_reg_dest" "=r")
(sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
(sign_extend:SI (match_operand:HI 1 "arith_reg_operand" "r")))]
"TARGET_SH1"
"exts.w %1,%0"
[(set_attr "type" "arith")])