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[PATCH v2] sh: Correct NaN signalling bit and propagation rules [PR111814] 

As per architecture, SuperH has a reversed NaN signalling bit
vs IEEE754-2008, it also has a NaN propgation rule similar to
MIPS style.

Use mips style float format and mode for all float types, and
correct sfp-machine header accordingly.

	PR target/111814

gcc/ChangeLog:

	* config/sh/sh-modes.def (RESET_FLOAT_FORMAT): Use mips format.
	(FLOAT_MODE): Use mips mode.

libgcc/ChangeLog:

	* config/sh/sfp-machine.h (_FP_NANFRAC_B): Reverse signaling bit.
	(_FP_NANFRAC_H): Likewise.
	(_FP_NANFRAC_S): Likewise.
	(_FP_NANFRAC_D): Likewise.
	(_FP_NANFRAC_Q): Likewise.
	(_FP_KEEPNANFRACP): Enable for target.
	(_FP_QNANNEGATEDP): Enable for target.
	(_FP_CHOOSENAN): Port from MIPS.

gcc/testsuite/ChangeLog:

	* gcc.target/sh/pr111814.c: New test.
This commit is contained in:
Jiaxun Yang 2025-04-19 08:07:58 -06:00 committed by Jeff Law
parent 6beb0a14aa
commit 2a643f55f5
3 changed files with 35 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
gcc/config/sh/sh-modes.def
View File

@ -17,6 +17,12 @@ You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
/* SH has the same reversed quiet bit as MIPS. */
RESET_FLOAT_FORMAT (SF, mips_single_format);
RESET_FLOAT_FORMAT (DF, mips_double_format);
/* TFmode: IEEE quad floating point (software). */
FLOAT_MODE (TF, 16, mips_quad_format);
/* Vector modes. */
VECTOR_MODE (INT, QI, 2); /* V2QI */
VECTOR_MODES (INT, 4); /* V4QI V2HI */

7
gcc/testsuite/gcc.target/sh/pr111814.c Normal file
View File

@ -0,0 +1,7 @@
/* Verify that __builtin_nan("") produces a constant matches
architecture specification. */
/* { dg-do compile } */
double d = __builtin_nan ("");
/* { dg-final { scan-assembler "\t.long\t-1\n\t.long\t2146959359\n" } } */

34
libgcc/config/sh/sfp-machine.h
View File

@ -39,11 +39,11 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
#define _FP_DIV_MEAT_D(R,X,Y) _FP_DIV_MEAT_2_udiv(D,R,X,Y)
#define _FP_DIV_MEAT_Q(R,X,Y) _FP_DIV_MEAT_4_udiv(Q,R,X,Y)
#define _FP_NANFRAC_B _FP_QNANBIT_B
#define _FP_NANFRAC_H _FP_QNANBIT_H
#define _FP_NANFRAC_S _FP_QNANBIT_S
#define _FP_NANFRAC_D _FP_QNANBIT_D, 0
#define _FP_NANFRAC_Q _FP_QNANBIT_Q, 0, 0, 0
#define _FP_NANFRAC_B (_FP_QNANBIT_B - 1)
#define _FP_NANFRAC_H (_FP_QNANBIT_H - 1)
#define _FP_NANFRAC_S (_FP_QNANBIT_S - 1)
#define _FP_NANFRAC_D (_FP_QNANBIT_D - 1), -1
#define _FP_NANFRAC_Q (_FP_QNANBIT_Q - 1), -1, -1, -1
/* The type of the result of a floating point comparison. This must
match __libgcc_cmp_return__ in GCC for the target. */
@ -56,14 +56,24 @@ typedef int __gcc_CMPtype __attribute__ ((mode (__libgcc_cmp_return__)));
#define _FP_NANSIGN_D 0
#define _FP_NANSIGN_Q 0
#define _FP_KEEPNANFRACP 0
#define _FP_QNANNEGATEDP 0
#define _FP_KEEPNANFRACP 1
#define _FP_QNANNEGATEDP 1
#define _FP_CHOOSENAN(fs, wc, R, X, Y, OP) \
do { \
R##_s = _FP_NANSIGN_##fs; \
_FP_FRAC_SET_##wc(R,_FP_NANFRAC_##fs); \
R##_c = FP_CLS_NAN; \
/* X is chosen unless one of the NaNs is sNaN. */
# define _FP_CHOOSENAN(fs, wc, R, X, Y, OP) \
do { \
if ((_FP_FRAC_HIGH_RAW_##fs(X) | \
_FP_FRAC_HIGH_RAW_##fs(Y)) & _FP_QNANBIT_##fs) \
{ \
R##_s = _FP_NANSIGN_##fs; \
_FP_FRAC_SET_##wc(R,_FP_NANFRAC_##fs); \
} \
else \
{ \
R##_s = X##_s; \
_FP_FRAC_COPY_##wc(R,X); \
} \
R##_c = FP_CLS_NAN; \
} while (0)
#define _FP_TININESS_AFTER_ROUNDING 1