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re PR target/51681 (ICE in gcc.dg/torture/vshuf-v2si.c on ia64) 

PR target/51681
	* config/ia64/ia64.c (expand_vec_perm_shrp): Use correct operands
	for shrp pattern.  Correctly handle and fixup shift variable.
	Return false when shift > nelt for BYTES_BIG_ENDIAN target.

From-SVN: r182931
This commit is contained in:
Uros Bizjak 2012-01-05 22:50:20 +01:00
parent a32e5e9357
commit 2d130b315d
2 changed files with 25 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
gcc/ChangeLog
View File

@ -1,3 +1,10 @@
2012-01-05 Uros Bizjak <ubizjak@gmail.com>
PR target/51681
* config/ia64/ia64.c (expand_vec_perm_shrp): Use correct operands
for shrp pattern. Correctly handle and fixup shift variable.
Return false when shift > nelt for BYTES_BIG_ENDIAN target.
2012-01-05 Jakub Jelinek <jakub@redhat.com>
PR debug/51762
@ -42,8 +49,7 @@
2012-01-05 Jakub Jelinek <jakub@redhat.com>
PR middle-end/51761
* gimple.h (struct gimplify_ctx): Add in_cleanup_point_expr
field.
* gimple.h (struct gimplify_ctx): Add in_cleanup_point_expr field.
* gimplify.c (gimplify_cleanup_point_expr): Save and set
in_cleanup_point_expr before gimplify_stmt call and restore it
afterwards.
@ -183,17 +189,15 @@
PR tree-optimization/49651
* tree-ssa-structalias.c (type_can_have_subvars): New function.
(var_can_have_subvars): Use it.
(get_constraint_for_1): Only consider subfields if there
can be any.
(get_constraint_for_1): Only consider subfields if there can be any.
2012-01-03 Jakub Jelinek <jakub@redhat.com>
PR bootstrap/51725
* cselib.c (new_elt_loc_list): When moving locs from one
cselib_val to its new canonical_cselib_val and the
cselib_val was in first_containing_mem chain, but
the canonical_cselib_val was not, add the latter into the
chain.
* cselib.c (new_elt_loc_list): When moving locs from one cselib_val
to its new canonical_cselib_val and the cselib_val was in
first_containing_mem chain, but the canonical_cselib_val was not,
add the latter into the chain.
(cselib_invalidate_mem): Compare canonical_cselib_val of
addr_list chain elt with v.

18
gcc/config/ia64/ia64.c
View File

@ -11085,7 +11085,7 @@ static bool
expand_vec_perm_shrp (struct expand_vec_perm_d *d)
{
unsigned i, nelt = d->nelt, shift, mask;
rtx tmp, op0, op1;;
rtx tmp, hi, lo;
/* ??? Don't force V2SFmode into the integer registers. */
if (d->vmode == V2SFmode)
@ -11094,6 +11094,9 @@ expand_vec_perm_shrp (struct expand_vec_perm_d *d)
mask = (d->one_operand_p ? nelt - 1 : 2 * nelt - 1);
shift = d->perm[0];
if (BYTES_BIG_ENDIAN && shift > nelt)
return false;
for (i = 1; i < nelt; ++i)
if (d->perm[i] != ((shift + i) & mask))
return false;
@ -11101,6 +11104,11 @@ expand_vec_perm_shrp (struct expand_vec_perm_d *d)
if (d->testing_p)
return true;
hi = shift < nelt ? d->op1 : d->op0;
lo = shift < nelt ? d->op0 : d->op1;
shift %= nelt;
shift *= GET_MODE_UNIT_SIZE (d->vmode) * BITS_PER_UNIT;
/* We've eliminated the shift 0 case via expand_vec_perm_identity. */
@ -11113,11 +11121,9 @@ expand_vec_perm_shrp (struct expand_vec_perm_d *d)
shift = 64 - shift;
tmp = gen_reg_rtx (DImode);
op0 = (shift < nelt ? d->op0 : d->op1);
op1 = (shift < nelt ? d->op1 : d->op0);
op0 = gen_lowpart (DImode, op0);
op1 = gen_lowpart (DImode, op1);
emit_insn (gen_shrp (tmp, op0, op1, GEN_INT (shift)));
hi = gen_lowpart (DImode, hi);
lo = gen_lowpart (DImode, lo);
emit_insn (gen_shrp (tmp, hi, lo, GEN_INT (shift)));
emit_move_insn (d->target, gen_lowpart (d->vmode, tmp));
return true;