mirror of git://gcc.gnu.org/git/gcc.git
sse.md (*vec_extract<ssevecmodelower>_0): Merge from sse2_stored and *sse2_storeq_rex64 using SWI48 mode iterator.
* config/i386/sse.md (*vec_extract<ssevecmodelower>_0): Merge from sse2_stored and *sse2_storeq_rex64 using SWI48 mode iterator. Add m->r,x alternatives. (*vec_extract<ssevecmodelower>_0 splitters): Merge V2DI and V4SI splitters using SWI48x mode iterator. (*vec_extract_v2di_0_sse): Rename from *sse2_storeq. Disable for TARGET_64BIT. Add m->x alternative. (*vec_extractv4si_mem): Rename from *vec_ext_v4si_mem. Add o->x alternative. Enable for TARGET_SSE. (sse_storeq): Remove expander. (*vec_extractv2di_1): Enable for TARGET_SSE. Split alternatives with memory input operand. (*vec_extractv2di_1 splitter): New. (*vec_extractv4sf_mem): Rename from *vec_extract_v4sf_mem. * config/i386/i386.md (ssevecmodelower): New mode attribute. From-SVN: r198611
This commit is contained in:
Uros Bizjak
parent
f0470cc59f
commit
3095685e6d
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@ -1,3 +1,21 @@
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2013-05-05 Uros Bizjak <ubizjak@gmail.com>
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* config/i386/sse.md (*vec_extract<ssevecmodelower>_0): Merge
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from sse2_stored and *sse2_storeq_rex64 using SWI48 mode iterator.
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Add m->r,x alternatives.
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(*vec_extract<ssevecmodelower>_0 splitters): Merge V2DI and V4SI
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splitters using SWI48x mode iterator.
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(*vec_extract_v2di_0_sse): Rename from *sse2_storeq. Disable for
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TARGET_64BIT. Add m->x alternative.
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(*vec_extractv4si_mem): Rename from *vec_ext_v4si_mem.
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Add o->x alternative. Enable for TARGET_SSE.
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(sse_storeq): Remove expander.
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(*vec_extractv2di_1): Enable for TARGET_SSE. Split alternatives
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with memory input operand.
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(*vec_extractv2di_1 splitter): New.
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(*vec_extractv4sf_mem): Rename from *vec_extract_v4sf_mem.
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* config/i386/i386.md (ssevecmodelower): New mode attribute.
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2013-05-04 Segher Boessenkool <segher@kernel.crashing.org>
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* config/rs6000/rs6000.c (INT_P): Reformat. Delete obsolete comment.
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@ -14,8 +32,7 @@
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logical_const_operand): Delete "CONST_DOUBLE" case.
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* config/rs6000/rs6000.c (num_insns_constant_wide): Delete
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"HOST_BITS_PER_WIDE_INT == 64" test.
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(num_insns_constant): Ditto. Delete CONST_DOUBLE DImode/VOIDmode
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case.
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(num_insns_constant): Ditto. Delete CONST_DOUBLE DImode/VOIDmode case.
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(build_mask64_2_operands): Delete "HOST_BITS_PER_WIDE_INT >= 64" test.
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(rs6000_emit_set_const): Delete CONST_DOUBLE case.
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(rs6000_emit_set_long_const): Delete "HOST_BITS_PER_WIDE_INT >= 64"
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@ -62,8 +79,8 @@
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2013-05-03 Guozhi Wei <carrot@google.com>
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* coverage.c (coverage_obj_init): Move the construction of gcov
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constructor to
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(build_init_ctor): here.
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constructor to ...
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(build_init_ctor): ... here.
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2013-05-03 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
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@ -127,9 +144,8 @@
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2013-05-03 Jakub Jelinek <jakub@redhat.com>
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PR rtl-optimization/57130
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* combine.c (make_compound_operation) <case SUBREG>: Pass
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SET instead of COMPARE as in_code to the recursive call
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if needed.
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* combine.c (make_compound_operation) <case SUBREG>: Pass SET instead
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of COMPARE as in_code to the recursive call if needed.
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2013-05-03 Uros Bizjak <ubizjak@gmail.com>
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@ -929,6 +929,8 @@
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;; SSE vector mode corresponding to a scalar mode
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(define_mode_attr ssevecmode
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[(QI "V16QI") (HI "V8HI") (SI "V4SI") (DI "V2DI") (SF "V4SF") (DF "V2DF")])
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(define_mode_attr ssevecmodelower
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[(QI "v16qi") (HI "v8hi") (SI "v4si") (DI "v2di") (SF "v4sf") (DF "v2df")])
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;; Instruction suffix for REX 64bit operators.
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(define_mode_attr rex64suffix [(SI "") (DI "{q}")])
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@ -4347,11 +4347,11 @@
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(set_attr "prefix" "maybe_vex,*,*")
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(set_attr "mode" "V4SF,*,*")])
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(define_insn_and_split "*vec_extract_v4sf_mem"
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(define_insn_and_split "*vec_extractv4sf_mem"
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[(set (match_operand:SF 0 "register_operand" "=x,*r,f")
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(vec_select:SF
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(match_operand:V4SF 1 "memory_operand" "o,o,o")
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(parallel [(match_operand 2 "const_0_to_3_operand" "n,n,n")])))]
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(vec_select:SF
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(match_operand:V4SF 1 "memory_operand" "o,o,o")
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(parallel [(match_operand 2 "const_0_to_3_operand" "n,n,n")])))]
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"TARGET_SSE"
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"#"
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"&& reload_completed"
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@ -7014,7 +7014,7 @@
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(set_attr "prefix" "maybe_vex")
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(set_attr "mode" "TI")])
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;; It must come before *vec_extractv2di_1_rex64 since it is preferred.
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;; It must come before *vec_extractv2di_1 since it is preferred.
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(define_insn "*sse4_1_pextrq"
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[(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
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(vec_select:DI
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@ -7357,98 +7357,84 @@
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(set_attr "prefix" "maybe_vex,maybe_vex,orig,orig,vex")
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(set_attr "mode" "TI,TI,V4SF,SF,SF")])
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(define_insn_and_split "sse2_stored"
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[(set (match_operand:SI 0 "nonimmediate_operand" "=xm,r")
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(vec_select:SI
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(match_operand:V4SI 1 "register_operand" "x,Yj")
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(define_insn "*vec_extract<ssevecmodelower>_0"
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[(set (match_operand:SWI48 0 "nonimmediate_operand" "=x,m,r ,r")
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(vec_select:SWI48
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(match_operand:<ssevecmode> 1 "nonimmediate_operand" "xm,x,Yj,m")
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(parallel [(const_int 0)])))]
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"TARGET_SSE"
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"#"
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"&& reload_completed
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&& (TARGET_INTER_UNIT_MOVES_FROM_VEC
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|| MEM_P (operands [0])
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|| !GENERAL_REGNO_P (true_regnum (operands [0])))"
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[(set (match_dup 0) (match_dup 1))]
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"operands[1] = gen_rtx_REG (SImode, REGNO (operands[1]));")
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"TARGET_SSE && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
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"#")
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(define_insn_and_split "*vec_ext_v4si_mem"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(vec_select:SI
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(match_operand:V4SI 1 "memory_operand" "o")
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(parallel [(match_operand 2 "const_0_to_3_operand")])))]
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""
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"#"
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"reload_completed"
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[(const_int 0)]
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{
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int i = INTVAL (operands[2]);
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emit_move_insn (operands[0], adjust_address (operands[1], SImode, i*4));
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DONE;
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})
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(define_expand "sse_storeq"
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[(set (match_operand:DI 0 "nonimmediate_operand")
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(define_insn "*vec_extractv2di_0_sse"
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[(set (match_operand:DI 0 "nonimmediate_operand" "=x,m")
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(vec_select:DI
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(match_operand:V2DI 1 "register_operand")
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(match_operand:V2DI 1 "nonimmediate_operand" "xm,x")
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(parallel [(const_int 0)])))]
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"TARGET_SSE")
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(define_insn "*sse2_storeq_rex64"
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[(set (match_operand:DI 0 "nonimmediate_operand" "=xm,*r,r")
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(vec_select:DI
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(match_operand:V2DI 1 "nonimmediate_operand" "x,Yj,o")
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(parallel [(const_int 0)])))]
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"TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
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"@
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#
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#
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mov{q}\t{%1, %0|%0, %1}"
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[(set_attr "type" "*,*,imov")
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(set_attr "mode" "*,*,DI")])
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(define_insn "*sse2_storeq"
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[(set (match_operand:DI 0 "nonimmediate_operand" "=xm")
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(vec_select:DI
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(match_operand:V2DI 1 "register_operand" "x")
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(parallel [(const_int 0)])))]
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"TARGET_SSE"
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"TARGET_SSE && !TARGET_64BIT
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&& !(MEM_P (operands[0]) && MEM_P (operands[1]))"
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"#")
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(define_split
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[(set (match_operand:DI 0 "nonimmediate_operand")
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(vec_select:DI
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(match_operand:V2DI 1 "register_operand")
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[(set (match_operand:SWI48x 0 "register_operand")
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(vec_select:SWI48x
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(match_operand:<ssevecmode> 1 "memory_operand")
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(parallel [(const_int 0)])))]
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"TARGET_SSE
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&& reload_completed
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&& (TARGET_INTER_UNIT_MOVES_FROM_VEC
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|| MEM_P (operands [0])
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|| !GENERAL_REGNO_P (true_regnum (operands [0])))"
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"TARGET_SSE && reload_completed"
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[(set (match_dup 0) (match_dup 1))]
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"operands[1] = gen_rtx_REG (DImode, REGNO (operands[1]));")
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"operands[1] = adjust_address (operands[1], <MODE>mode, 0);")
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(define_split
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[(set (match_operand:SWI48x 0 "nonimmediate_operand")
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(vec_select:SWI48x
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(match_operand:<ssevecmode> 1 "register_operand")
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(parallel [(const_int 0)])))]
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"TARGET_SSE && reload_completed
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&& (TARGET_INTER_UNIT_MOVES_FROM_VEC
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|| !GENERAL_REG_P (operands [0]))"
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[(set (match_dup 0) (match_dup 1))]
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"operands[1] = gen_rtx_REG (<MODE>mode, REGNO (operands[1]));")
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(define_insn_and_split "*vec_extractv4si_mem"
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[(set (match_operand:SI 0 "register_operand" "=x,r")
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(vec_select:SI
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(match_operand:V4SI 1 "memory_operand" "o,o")
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(parallel [(match_operand 2 "const_0_to_3_operand")])))]
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"TARGET_SSE"
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"#"
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"&& reload_completed"
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[(set (match_dup 0) (match_dup 1))]
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{
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operands[1] = adjust_address (operands[1], SImode, INTVAL (operands[2]) * 4);
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})
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(define_insn "*vec_extractv2di_1"
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[(set (match_operand:DI 0 "nonimmediate_operand" "=m,x,x,x,x,x,r")
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[(set (match_operand:DI 0 "nonimmediate_operand" "=m,x,x,x,x,r")
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(vec_select:DI
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(match_operand:V2DI 1 "nonimmediate_operand" " x,0,x,o,x,o,o")
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(match_operand:V2DI 1 "nonimmediate_operand" " x,0,x,x,o,o")
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(parallel [(const_int 1)])))]
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"(TARGET_64BIT || TARGET_SSE)
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&& !(MEM_P (operands[0]) && MEM_P (operands[1]))"
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"TARGET_SSE && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
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"@
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%vmovhps\t{%1, %0|%0, %1}
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psrldq\t{$8, %0|%0, 8}
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vpsrldq\t{$8, %1, %0|%0, %1, 8}
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%vmovq\t{%H1, %0|%0, %H1}
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movhlps\t{%1, %0|%0, %1}
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movlps\t{%H1, %0|%0, %H1}
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mov{q}\t{%H1, %0|%0, %H1}"
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[(set_attr "isa" "*,sse2_noavx,avx,sse2,noavx,noavx,x64")
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(set_attr "type" "ssemov,sseishft1,sseishft1,ssemov,ssemov,ssemov,imov")
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(set_attr "length_immediate" "*,1,1,*,*,*,*")
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(set_attr "memory" "*,none,none,*,*,*,*")
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(set_attr "prefix" "maybe_vex,orig,vex,maybe_vex,orig,orig,orig")
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(set_attr "mode" "V2SF,TI,TI,TI,V4SF,V2SF,DI")])
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#
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#"
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[(set_attr "isa" "*,sse2_noavx,avx,noavx,*,x64")
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(set_attr "type" "ssemov,sseishft1,sseishft1,ssemov,ssemov,imov")
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(set_attr "length_immediate" "*,1,1,*,*,*")
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(set_attr "memory" "*,none,none,*,*,*")
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(set_attr "prefix" "maybe_vex,orig,vex,orig,*,*")
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(set_attr "mode" "V2SF,TI,TI,V4SF,DI,DI")])
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(define_split
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[(set (match_operand:DI 0 "register_operand")
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(vec_select:DI
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(match_operand:V2DI 1 "memory_operand")
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(parallel [(const_int 1)])))]
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"TARGET_SSE && reload_completed"
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[(set (match_dup 0) (match_dup 1))]
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"operands[1] = adjust_address (operands[1], DImode, 8);")
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(define_insn "*vec_dupv4si"
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[(set (match_operand:V4SI 0 "register_operand" "=x,x,x")
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