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sparc.h (CANNOT_CHANGE_MODE_CLASS): In 64-bit mode, disallow changes from SFmode to mode with different size in FP regs. 

* config/sparc/sparc.h (CANNOT_CHANGE_MODE_CLASS): In 64-bit mode,
	disallow changes from SFmode to mode with different size in FP regs.

From-SVN: r184144
This commit is contained in:
Eric Botcazou 2012-02-12 20:42:45 +00:00
parent 5b4a7d0d8a
commit 31d7b43969
2 changed files with 13 additions and 5 deletions
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7
gcc/ChangeLog
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@ -1,4 +1,9 @@
2012-01-29 Robert Millan <rmh@gnu.org> 2012-02-12 Eric Botcazou <ebotcazou@adacore.com>
* config/sparc/sparc.h (CANNOT_CHANGE_MODE_CLASS): In 64-bit mode,
disallow changes from SFmode to mode with different size in FP regs.
2012-02-12 Robert Millan <rmh@gnu.org>
Gerald Pfeifer <gerald@pfeifer.com> Gerald Pfeifer <gerald@pfeifer.com>
* ginclude/stddef.h [__FreeBSD_kernel__] (__size_t): Do not define. * ginclude/stddef.h [__FreeBSD_kernel__] (__size_t): Do not define.

11
gcc/config/sparc/sparc.h
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@ -894,18 +894,21 @@ extern enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
#define REGNO_REG_CLASS(REGNO) sparc_regno_reg_class[(REGNO)] #define REGNO_REG_CLASS(REGNO) sparc_regno_reg_class[(REGNO)]
/* Defines invalid mode changes. Borrowed from pa64-regs.h. /* Defines invalid mode changes. Borrowed from the PA port.
SImode loads to floating-point registers are not zero-extended. SImode loads to floating-point registers are not zero-extended.
The definition for LOAD_EXTEND_OP specifies that integer loads The definition for LOAD_EXTEND_OP specifies that integer loads
narrower than BITS_PER_WORD will be zero-extended. As a result, narrower than BITS_PER_WORD will be zero-extended. As a result,
we inhibit changes from SImode unless they are to a mode that is we inhibit changes from SImode unless they are to a mode that is
identical in size. */ identical in size.
Likewise for SFmode, since word-mode paradoxical subregs are
problematic on big-endian architectures. */
#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
(TARGET_ARCH64 \ (TARGET_ARCH64 \
&& (FROM) == SImode \ && GET_MODE_SIZE (FROM) == 4 \
&& GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \ && GET_MODE_SIZE (TO) != 4 \
? reg_classes_intersect_p (CLASS, FP_REGS) : 0) ? reg_classes_intersect_p (CLASS, FP_REGS) : 0)
/* This is the order in which to allocate registers normally. /* This is the order in which to allocate registers normally.