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* config/aarch64/aarch64.c (aarch64_classify_address) 

(aarch64_legitimize_reload_address): Support full addressing modes
	for vector modes.
	* config/aarch64/aarch64.md (mov<mode>, movmisalign<mode>)
	(*aarch64_simd_mov<mode>, *aarch64_simd_mov<mode>): Relax predicates.

From-SVN: r211211
This commit is contained in:
Bin Cheng 2014-06-04 03:45:50 +00:00 committed by Bin Cheng
parent 1b1b580c5b
commit 348d4b0a54
3 changed files with 21 additions and 13 deletions
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8
gcc/ChangeLog
View File

@ -1,3 +1,11 @@
2014-06-04 Bin Cheng <bin.cheng@arm.com>
* config/aarch64/aarch64.c (aarch64_classify_address)
(aarch64_legitimize_reload_address): Support full addressing modes
for vector modes.
* config/aarch64/aarch64.md (mov<mode>, movmisalign<mode>)
(*aarch64_simd_mov<mode>, *aarch64_simd_mov<mode>): Relax predicates.
2014-06-03 Andrew Pinski <apinski@cavium.com>
* config/aarch64/aarch64.c (aarch64_if_then_else_costs): Allow non comparisons

16
gcc/config/aarch64/aarch64-simd.md
View File

@ -19,8 +19,8 @@
;; <http://www.gnu.org/licenses/>.
(define_expand "mov<mode>"
[(set (match_operand:VALL 0 "aarch64_simd_nonimmediate_operand" "")
(match_operand:VALL 1 "aarch64_simd_general_operand" ""))]
[(set (match_operand:VALL 0 "nonimmediate_operand" "")
(match_operand:VALL 1 "general_operand" ""))]
"TARGET_SIMD"
"
if (GET_CODE (operands[0]) == MEM)
@ -29,8 +29,8 @@
)
(define_expand "movmisalign<mode>"
[(set (match_operand:VALL 0 "aarch64_simd_nonimmediate_operand" "")
(match_operand:VALL 1 "aarch64_simd_general_operand" ""))]
[(set (match_operand:VALL 0 "nonimmediate_operand" "")
(match_operand:VALL 1 "general_operand" ""))]
"TARGET_SIMD"
{
/* This pattern is not permitted to fail during expansion: if both arguments
@ -91,9 +91,9 @@
)
(define_insn "*aarch64_simd_mov<mode>"
[(set (match_operand:VD 0 "aarch64_simd_nonimmediate_operand"
[(set (match_operand:VD 0 "nonimmediate_operand"
"=w, m, w, ?r, ?w, ?r, w")
(match_operand:VD 1 "aarch64_simd_general_operand"
(match_operand:VD 1 "general_operand"
"m, w, w, w, r, r, Dn"))]
"TARGET_SIMD
&& (register_operand (operands[0], <MODE>mode)
@ -119,9 +119,9 @@
)
(define_insn "*aarch64_simd_mov<mode>"
[(set (match_operand:VQ 0 "aarch64_simd_nonimmediate_operand"
[(set (match_operand:VQ 0 "nonimmediate_operand"
"=w, m, w, ?r, ?w, ?r, w")
(match_operand:VQ 1 "aarch64_simd_general_operand"
(match_operand:VQ 1 "general_operand"
"m, w, w, w, r, r, Dn"))]
"TARGET_SIMD
&& (register_operand (operands[0], <MODE>mode)

10
gcc/config/aarch64/aarch64.c
View File

@ -3158,11 +3158,11 @@ aarch64_classify_address (struct aarch64_address_info *info,
enum rtx_code code = GET_CODE (x);
rtx op0, op1;
bool allow_reg_index_p =
outer_code != PARALLEL && GET_MODE_SIZE(mode) != 16;
outer_code != PARALLEL && (GET_MODE_SIZE (mode) != 16
|| aarch64_vector_mode_supported_p (mode));
/* Don't support anything other than POST_INC or REG addressing for
AdvSIMD. */
if (aarch64_vector_mode_p (mode)
if (aarch64_vect_struct_mode_p (mode)
&& (code != POST_INC && code != REG))
return false;
@ -4092,8 +4092,8 @@ aarch64_legitimize_reload_address (rtx *x_p,
{
rtx x = *x_p;
/* Do not allow mem (plus (reg, const)) if vector mode. */
if (aarch64_vector_mode_p (mode)
/* Do not allow mem (plus (reg, const)) if vector struct mode. */
if (aarch64_vect_struct_mode_p (mode)
&& GET_CODE (x) == PLUS
&& REG_P (XEXP (x, 0))
&& CONST_INT_P (XEXP (x, 1)))