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mips-cpus.def: Add Octeon2. 

2011-12-13  Andrew Pinski  <apinski@cavium.com>
            Adam Nemet  <anemet@caviumnetworks.com>

	* config/mips/mips-cpus.def: Add Octeon2.
	* config/mips/mips-tables.opt: Regenerate.
	* config/mips/mips.md (define_attr "cpu"): Add Octeon2.
	* config/mips/driver-native.c (host_detect_local_cpu): Support Octeon2 also.
	* config/mips/octeon.md (octeon_arith): Add Octeon2.
	(octeon_condmove): Likewise.
	(octeon_load): Rename to ..
	(octeon_load_o1): this.
	(octeon_load_o2): New reserve.
	(octeon_cop_o2): New reserve.
	(octeon_store):  Match Octeon2 also.
	(octeon_brj): Rename to ..
	(octeon_brj_o1): this.
	(octeon_brj_o2): New reserve.
	(octeon_imul3): Rename to ...
	(octeon_imul3_o1): this.
	(octeon_imul3_o2): New reserve.
	(octeon_imul): Rename to ...
	(octeon_imul_o1): this.
	(octeon_imul_o2): New reserve.
	(octeon_mfhilo): Rename to ...
	(octeon_mfhilo_o1): This.
	(octeon_mfhilo_o2): New reserve.
	(octeon_imadd): Rename to ...
	(octeon_imadd_o1): this.
	(octeon_imadd_o2): New reserve.
	(octeon_idiv): Rename to ..
	(octeon_idiv_o1): This.
	(octeon_idiv_o2_si): New reserve.
	(octeon_idiv_o2_di): Likewise.
	(octeon_unknown): Match Octeon2 also.
	* config/mips/mips.c (mips_rtx_cost_data): Add Octeon2 cost data.
	(mips_issue_rate): Octeon2 can issue 2 at a time.
	* config/mips/mips.h (TARGET_OCTEON): Match Octeon2 also.
	(TARGET_OCTEON2): New define.
	(TUNE_OCTEON): Match Octeon2 also.

2011-12-13  Andrew Pinski  <apinski@cavium.com>
            Adam Nemet  <anemet@caviumnetworks.com>

	* gcc.target/mips/mips.exp (mips_option_groups): Fix debug.  Add
	-fdump-* options.
	* gcc.target/mips/octeon2-pipe-1.c: New testcase.
	* gcc.target/mips/octeon-pipe-1.c: New testcase.


Co-Authored-By: Adam Nemet <anemet@caviumnetworks.com>

From-SVN: r182300
This commit is contained in:
Andrew Pinski 2011-12-13 20:00:18 +00:00 committed by Andrew Pinski
parent e9619a8a00
commit 38a53a0e25
12 changed files with 155 additions and 14 deletions
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40
gcc/ChangeLog
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@ -1,3 +1,43 @@
2011-12-13 Andrew Pinski <apinski@cavium.com>
Adam Nemet <anemet@caviumnetworks.com>
* config/mips/mips-cpus.def: Add Octeon2.
* config/mips/mips-tables.opt: Regenerate.
* config/mips/mips.md (define_attr "cpu"): Add Octeon2.
* config/mips/driver-native.c (host_detect_local_cpu): Support Octeon2 also.
* config/mips/octeon.md (octeon_arith): Add Octeon2.
(octeon_condmove): Likewise.
(octeon_load): Rename to ..
(octeon_load_o1): this.
(octeon_load_o2): New reserve.
(octeon_cop_o2): New reserve.
(octeon_store): Match Octeon2 also.
(octeon_brj): Rename to ..
(octeon_brj_o1): this.
(octeon_brj_o2): New reserve.
(octeon_imul3): Rename to ...
(octeon_imul3_o1): this.
(octeon_imul3_o2): New reserve.
(octeon_imul): Rename to ...
(octeon_imul_o1): this.
(octeon_imul_o2): New reserve.
(octeon_mfhilo): Rename to ...
(octeon_mfhilo_o1): This.
(octeon_mfhilo_o2): New reserve.
(octeon_imadd): Rename to ...
(octeon_imadd_o1): this.
(octeon_imadd_o2): New reserve.
(octeon_idiv): Rename to ..
(octeon_idiv_o1): This.
(octeon_idiv_o2_si): New reserve.
(octeon_idiv_o2_di): Likewise.
(octeon_unknown): Match Octeon2 also.
* config/mips/mips.c (mips_rtx_cost_data): Add Octeon2 cost data.
(mips_issue_rate): Octeon2 can issue 2 at a time.
* config/mips/mips.h (TARGET_OCTEON): Match Octeon2 also.
(TARGET_OCTEON2): New define.
(TUNE_OCTEON): Match Octeon2 also.
2011-12-13 Richard Henderson <rth@redhat.com>
* config/sparc/tso.h: New file.

2
gcc/config/mips/driver-native.c
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@ -125,6 +125,8 @@ host_detect_local_cpu (int argc, const char **argv)
cpu = "sb1";
else if (strstr (buf, "R5000") != NULL)
cpu = "r5000";
else if (strstr (buf, "Octeon II") != NULL)
cpu = "octeon2";
else if (strstr (buf, "Octeon") != NULL)
cpu = "octeon";
break;

1
gcc/config/mips/mips-cpus.def
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@ -146,3 +146,4 @@ MIPS_CPU ("loongson3a", PROCESSOR_LOONGSON_3A, 64, PTF_AVOID_BRANCHLIKELY)
/* MIPS64 Release 2 processors. */
MIPS_CPU ("octeon", PROCESSOR_OCTEON, 65, PTF_AVOID_BRANCHLIKELY)
MIPS_CPU ("octeon+", PROCESSOR_OCTEON, 65, PTF_AVOID_BRANCHLIKELY)
MIPS_CPU ("octeon2", PROCESSOR_OCTEON2, 65, PTF_AVOID_BRANCHLIKELY)

3
gcc/config/mips/mips-tables.opt
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@ -606,3 +606,6 @@ Enum(mips_arch_opt_value) String(octeon) Value(80) Canonical
EnumValue
Enum(mips_arch_opt_value) String(octeon+) Value(81) Canonical
EnumValue
Enum(mips_arch_opt_value) String(octeon2) Value(82) Canonical

11
gcc/config/mips/mips.c
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@ -879,6 +879,16 @@ static const struct mips_rtx_cost_data
COSTS_N_INSNS (72), /* int_div_di */
1, /* branch_cost */
4 /* memory_latency */
},
/* Octeon II */
{
SOFT_FP_COSTS,
COSTS_N_INSNS (6), /* int_mult_si */
COSTS_N_INSNS (6), /* int_mult_di */
COSTS_N_INSNS (18), /* int_div_si */
COSTS_N_INSNS (35), /* int_div_di */
4, /* branch_cost */
4 /* memory_latency */
},
{ /* R3900 */
COSTS_N_INSNS (2), /* fp_add */
@ -12038,6 +12048,7 @@ mips_issue_rate (void)
case PROCESSOR_R7000:
case PROCESSOR_R9000:
case PROCESSOR_OCTEON:
case PROCESSOR_OCTEON2:
return 2;
case PROCESSOR_SB1:

7
gcc/config/mips/mips.h
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@ -222,7 +222,9 @@ struct mips_cpu_info {
#define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
#define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
#define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
#define TARGET_OCTEON (mips_arch == PROCESSOR_OCTEON)
#define TARGET_OCTEON (mips_arch == PROCESSOR_OCTEON \
|| mips_arch == PROCESSOR_OCTEON2)
#define TARGET_OCTEON2 (mips_arch == PROCESSOR_OCTEON2)
#define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
|| mips_arch == PROCESSOR_SB1A)
#define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
@ -250,7 +252,8 @@ struct mips_cpu_info {
#define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
#define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
#define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
#define TUNE_OCTEON (mips_tune == PROCESSOR_OCTEON)
#define TUNE_OCTEON (mips_tune == PROCESSOR_OCTEON \
|| mips_tune == PROCESSOR_OCTEON2)
#define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
|| mips_tune == PROCESSOR_SB1A)

1
gcc/config/mips/mips.md
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@ -42,6 +42,7 @@
loongson_3a
m4k
octeon
octeon2
r3900
r6000
r4000

71
gcc/config/mips/octeon.md
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@ -30,59 +30,108 @@
(define_cpu_unit "octeon_mult" "octeon_mult")
(define_insn_reservation "octeon_arith" 1
(and (eq_attr "cpu" "octeon")
(and (eq_attr "cpu" "octeon,octeon2")
(eq_attr "type" "arith,const,logical,move,shift,signext,slt,nop"))
"octeon_pipe0 | octeon_pipe1")
(define_insn_reservation "octeon_condmove" 2
(and (eq_attr "cpu" "octeon")
(and (eq_attr "cpu" "octeon,octeon2")
(eq_attr "type" "condmove"))
"octeon_pipe0 | octeon_pipe1")
(define_insn_reservation "octeon_load" 2
(define_insn_reservation "octeon_load_o1" 2
(and (eq_attr "cpu" "octeon")
(eq_attr "type" "load,prefetch,mtc,mfc"))
"octeon_pipe0")
(define_insn_reservation "octeon_load_o2" 3
(and (eq_attr "cpu" "octeon2")
(eq_attr "type" "load,prefetch"))
"octeon_pipe0")
;; ??? memory-related cop0 reads are pipe0 with 3-cycle latency.
;; Front-end-related ones are 1-cycle on pipe1. Assume front-end for now.
(define_insn_reservation "octeon_cop_o2" 1
(and (eq_attr "cpu" "octeon2")
(eq_attr "type" "mtc,mfc"))
"octeon_pipe1")
(define_insn_reservation "octeon_store" 1
(and (eq_attr "cpu" "octeon")
(and (eq_attr "cpu" "octeon,octeon2")
(eq_attr "type" "store"))
"octeon_pipe0")
(define_insn_reservation "octeon_brj" 1
(define_insn_reservation "octeon_brj_o1" 1
(and (eq_attr "cpu" "octeon")
(eq_attr "type" "branch,jump,call,trap"))
"octeon_pipe0")
(define_insn_reservation "octeon_imul3" 5
(define_insn_reservation "octeon_brj_o2" 2
(and (eq_attr "cpu" "octeon2")
(eq_attr "type" "branch,jump,call,trap"))
"octeon_pipe1")
(define_insn_reservation "octeon_imul3_o1" 5
(and (eq_attr "cpu" "octeon")
(eq_attr "type" "imul3,pop,clz"))
"(octeon_pipe0 | octeon_pipe1) + octeon_mult")
(define_insn_reservation "octeon_imul" 2
(define_insn_reservation "octeon_imul3_o2" 6
(and (eq_attr "cpu" "octeon2")
(eq_attr "type" "imul3,pop,clz"))
"octeon_pipe1 + octeon_mult")
(define_insn_reservation "octeon_imul_o1" 2
(and (eq_attr "cpu" "octeon")
(eq_attr "type" "imul,mthilo"))
"(octeon_pipe0 | octeon_pipe1) + octeon_mult, octeon_mult")
(define_insn_reservation "octeon_mfhilo" 5
(define_insn_reservation "octeon_imul_o2" 1
(and (eq_attr "cpu" "octeon2")
(eq_attr "type" "imul,mthilo"))
"octeon_pipe1 + octeon_mult")
(define_insn_reservation "octeon_mfhilo_o1" 5
(and (eq_attr "cpu" "octeon")
(eq_attr "type" "mfhilo"))
"(octeon_pipe0 | octeon_pipe1) + octeon_mult")
(define_insn_reservation "octeon_imadd" 4
(define_insn_reservation "octeon_mfhilo_o2" 6
(and (eq_attr "cpu" "octeon2")
(eq_attr "type" "mfhilo"))
"octeon_pipe1 + octeon_mult")
(define_insn_reservation "octeon_imadd_o1" 4
(and (eq_attr "cpu" "octeon")
(eq_attr "type" "imadd"))
"(octeon_pipe0 | octeon_pipe1) + octeon_mult, octeon_mult*3")
(define_insn_reservation "octeon_idiv" 72
(define_insn_reservation "octeon_imadd_o2" 1
(and (eq_attr "cpu" "octeon2")
(eq_attr "type" "imadd"))
"octeon_pipe1 + octeon_mult")
(define_insn_reservation "octeon_idiv_o1" 72
(and (eq_attr "cpu" "octeon")
(eq_attr "type" "idiv"))
"(octeon_pipe0 | octeon_pipe1) + octeon_mult, octeon_mult*71")
(define_insn_reservation "octeon_idiv_o2_si" 18
(and (eq_attr "cpu" "octeon2")
(eq_attr "mode" "SI")
(eq_attr "type" "idiv"))
"octeon_pipe1 + octeon_mult, octeon_mult*17")
(define_insn_reservation "octeon_idiv_o2_di" 35
(and (eq_attr "cpu" "octeon2")
(eq_attr "mode" "DI")
(eq_attr "type" "idiv"))
"octeon_pipe1 + octeon_mult, octeon_mult*34")
;; Assume both pipes are needed for unknown and multiple-instruction
;; patterns.
(define_insn_reservation "octeon_unknown" 1
(and (eq_attr "cpu" "octeon")
(and (eq_attr "cpu" "octeon,octeon2")
(eq_attr "type" "unknown,multi"))
"octeon_pipe0 + octeon_pipe1")

8
gcc/testsuite/ChangeLog
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@ -1,3 +1,11 @@
2011-12-13 Andrew Pinski <apinski@cavium.com>
Adam Nemet <anemet@caviumnetworks.com>
* gcc.target/mips/mips.exp (mips_option_groups): Fix debug. Add
-fdump-* options.
* gcc.target/mips/octeon2-pipe-1.c: New testcase.
* gcc.target/mips/octeon-pipe-1.c: New testcase.
2011-12-11 Fabien Chêne <fabien@gcc.gnu.org>
PR c++/14258

3
gcc/testsuite/gcc.target/mips/mips.exp
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@ -226,7 +226,7 @@ set mips_option_groups {
abi "-mabi=.*"
addressing "addressing=.*"
arch "-mips([1-5]|32.*|64.*)|-march=.*|isa(|_rev)(=|<=|>=).*"
debug "-g*"
debug "-g.*"
dump_pattern "-dp"
endianness "-E(L|B)|-me(l|b)"
float "-m(hard|soft)-float"
@ -241,6 +241,7 @@ set mips_option_groups {
profiling "-pg"
small-data "-G[0-9]+"
warnings "-w"
dump "-fdump-.*"
}
# Add -mfoo/-mno-foo options to mips_option_groups.

11
gcc/testsuite/gcc.target/mips/octeon-pipe-1.c Normal file
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@ -0,0 +1,11 @@
/* Check that we use the octeon pipeline description. */
/* { dg-do compile } */
/* { dg-options "-O2 -march=octeon -fdump-rtl-sched2" } */
NOMIPS16 int f (int a, int b)
{
return a / b;
}
/* { dg-final { scan-rtl-dump "octeon_mult\\*71" "sched2" } } */
/* { dg-final { cleanup-tree-dump "sched2" } } */

11
gcc/testsuite/gcc.target/mips/octeon2-pipe-1.c Normal file
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@ -0,0 +1,11 @@
/* Check that we use the octeon2 pipeline description. */
/* { dg-do compile } */
/* { dg-options "-O2 -fdump-rtl-sched2 -march=octeon2" } */
NOMIPS16 int f (int a, int b)
{
return a / b;
}
/* { dg-final { scan-rtl-dump "octeon_mult\\*17" "sched2" } } */
/* { dg-final { cleanup-tree-dump "sched2" } } */