git
/
gcc
mirror of git://gcc.gnu.org/git/gcc.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

i386.c: Use SUBREG_P predicate. 

* config/i386/i386.c: Use SUBREG_P predicate.
	* config/i386/i386.md: Ditto.
	* config/i386/sse.md: Ditto.
	* config/i386/predicates.md: Ditto.

From-SVN: r226216
This commit is contained in:
Uros Bizjak 2015-07-25 14:47:35 +02:00 committed by Uros Bizjak
parent 0453025d3f
commit 3a6d28d685
5 changed files with 40 additions and 33 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
gcc/ChangeLog
View File

@ -1,3 +1,10 @@
2015-07-25 Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386.c: Use SUBREG_P predicate.
* config/i386/i386.md: Ditto.
* config/i386/sse.md: Ditto.
* config/i386/predicates.md: Ditto.
2015-07-25 Uros Bizjak <ubizjak@gmail.com> 2015-07-25 Uros Bizjak <ubizjak@gmail.com>
PR target/67004 PR target/67004

48
gcc/config/i386/i386.c
View File

@ -6180,7 +6180,7 @@ ix86_legitimate_combined_insn (rtx_insn *insn)
if (UNARY_P (op)) if (UNARY_P (op))
op = XEXP (op, 0); op = XEXP (op, 0);
if (GET_CODE (op) == SUBREG) if (SUBREG_P (op))
{ {
if (REG_P (SUBREG_REG (op)) if (REG_P (SUBREG_REG (op))
&& REGNO (SUBREG_REG (op)) < FIRST_PSEUDO_REGISTER) && REGNO (SUBREG_REG (op)) < FIRST_PSEUDO_REGISTER)
@ -9477,7 +9477,7 @@ ix86_check_movabs (rtx insn, int opnum)
set = XVECEXP (set, 0, 0); set = XVECEXP (set, 0, 0);
gcc_assert (GET_CODE (set) == SET); gcc_assert (GET_CODE (set) == SET);
mem = XEXP (set, opnum); mem = XEXP (set, opnum);
while (GET_CODE (mem) == SUBREG) while (SUBREG_P (mem))
mem = SUBREG_REG (mem); mem = SUBREG_REG (mem);
gcc_assert (MEM_P (mem)); gcc_assert (MEM_P (mem));
return volatile_ok || !MEM_VOLATILE_P (mem); return volatile_ok || !MEM_VOLATILE_P (mem);
@ -12895,7 +12895,7 @@ ix86_decompose_address (rtx addr, struct ix86_address *out)
they will be emitted with addr32 prefix. */ they will be emitted with addr32 prefix. */
if (TARGET_64BIT && GET_MODE (addr) == SImode) if (TARGET_64BIT && GET_MODE (addr) == SImode)
{ {
if (GET_CODE (addr) == SUBREG if (SUBREG_P (addr)
&& GET_MODE (SUBREG_REG (addr)) == DImode) && GET_MODE (SUBREG_REG (addr)) == DImode)
{ {
addr = SUBREG_REG (addr); addr = SUBREG_REG (addr);
@ -12906,7 +12906,7 @@ ix86_decompose_address (rtx addr, struct ix86_address *out)
if (REG_P (addr)) if (REG_P (addr))
base = addr; base = addr;
else if (GET_CODE (addr) == SUBREG) else if (SUBREG_P (addr))
{ {
if (REG_P (SUBREG_REG (addr))) if (REG_P (SUBREG_REG (addr)))
base = addr; base = addr;
@ -13024,7 +13024,7 @@ ix86_decompose_address (rtx addr, struct ix86_address *out)
{ {
if (REG_P (index)) if (REG_P (index))
; ;
else if (GET_CODE (index) == SUBREG else if (SUBREG_P (index)
&& REG_P (SUBREG_REG (index))) && REG_P (SUBREG_REG (index)))
; ;
else else
@ -13039,8 +13039,8 @@ ix86_decompose_address (rtx addr, struct ix86_address *out)
scale = INTVAL (scale_rtx); scale = INTVAL (scale_rtx);
} }
base_reg = base && GET_CODE (base) == SUBREG ? SUBREG_REG (base) : base; base_reg = base && SUBREG_P (base) ? SUBREG_REG (base) : base;
index_reg = index && GET_CODE (index) == SUBREG ? SUBREG_REG (index) : index; index_reg = index && SUBREG_P (index) ? SUBREG_REG (index) : index;
/* Avoid useless 0 displacement. */ /* Avoid useless 0 displacement. */
if (disp == const0_rtx && (base || index)) if (disp == const0_rtx && (base || index))
@ -13108,9 +13108,9 @@ ix86_address_cost (rtx x, machine_mode, addr_space_t, bool)
gcc_assert (ok); gcc_assert (ok);
if (parts.base && GET_CODE (parts.base) == SUBREG) if (parts.base && SUBREG_P (parts.base))
parts.base = SUBREG_REG (parts.base); parts.base = SUBREG_REG (parts.base);
if (parts.index && GET_CODE (parts.index) == SUBREG) if (parts.index && SUBREG_P (parts.index))
parts.index = SUBREG_REG (parts.index); parts.index = SUBREG_REG (parts.index);
/* Attempt to minimize number of registers in the address by increasing /* Attempt to minimize number of registers in the address by increasing
@ -13515,7 +13515,7 @@ ix86_validate_address_register (rtx op)
if (REG_P (op)) if (REG_P (op))
return op; return op;
else if (GET_CODE (op) == SUBREG) else if (SUBREG_P (op))
{ {
rtx reg = SUBREG_REG (op); rtx reg = SUBREG_REG (op);
@ -16727,7 +16727,7 @@ output_387_binary_op (rtx insn, rtx *operands)
static bool static bool
ix86_check_avx256_register (const_rtx exp) ix86_check_avx256_register (const_rtx exp)
{ {
if (GET_CODE (exp) == SUBREG) if (SUBREG_P (exp))
exp = SUBREG_REG (exp); exp = SUBREG_REG (exp);
return (REG_P (exp) return (REG_P (exp)
@ -17555,7 +17555,7 @@ ix86_expand_vector_move (machine_mode mode, rtx operands[])
if (can_create_pseudo_p () if (can_create_pseudo_p ()
&& register_operand (op0, mode) && register_operand (op0, mode)
&& (CONSTANT_P (op1) && (CONSTANT_P (op1)
|| (GET_CODE (op1) == SUBREG || (SUBREG_P (op1)
&& CONSTANT_P (SUBREG_REG (op1)))) && CONSTANT_P (SUBREG_REG (op1))))
&& !standard_sse_constant_p (op1)) && !standard_sse_constant_p (op1))
op1 = validize_mem (force_const_mem (mode, op1)); op1 = validize_mem (force_const_mem (mode, op1));
@ -17571,7 +17571,7 @@ ix86_expand_vector_move (machine_mode mode, rtx operands[])
/* ix86_expand_vector_move_misalign() does not like constants ... */ /* ix86_expand_vector_move_misalign() does not like constants ... */
if (CONSTANT_P (op1) if (CONSTANT_P (op1)
|| (GET_CODE (op1) == SUBREG || (SUBREG_P (op1)
&& CONSTANT_P (SUBREG_REG (op1)))) && CONSTANT_P (SUBREG_REG (op1))))
op1 = validize_mem (force_const_mem (mode, op1)); op1 = validize_mem (force_const_mem (mode, op1));
@ -18129,12 +18129,12 @@ ix86_expand_vector_logical_operator (enum rtx_code code, machine_mode mode,
rtx operands[]) rtx operands[])
{ {
rtx op1 = NULL_RTX, op2 = NULL_RTX; rtx op1 = NULL_RTX, op2 = NULL_RTX;
if (GET_CODE (operands[1]) == SUBREG) if (SUBREG_P (operands[1]))
{ {
op1 = operands[1]; op1 = operands[1];
op2 = operands[2]; op2 = operands[2];
} }
else if (GET_CODE (operands[2]) == SUBREG) else if (SUBREG_P (operands[2]))
{ {
op1 = operands[2]; op1 = operands[2];
op2 = operands[1]; op2 = operands[1];
@ -18146,7 +18146,7 @@ ix86_expand_vector_logical_operator (enum rtx_code code, machine_mode mode,
to cast them temporarily to integer vectors. */ to cast them temporarily to integer vectors. */
if (op1 if (op1
&& !TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL && !TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
&& ((GET_CODE (op2) == SUBREG || GET_CODE (op2) == CONST_VECTOR)) && (SUBREG_P (op2) || GET_CODE (op2) == CONST_VECTOR)
&& GET_MODE_CLASS (GET_MODE (SUBREG_REG (op1))) == MODE_VECTOR_FLOAT && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op1))) == MODE_VECTOR_FLOAT
&& GET_MODE_SIZE (GET_MODE (SUBREG_REG (op1))) == GET_MODE_SIZE (mode) && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op1))) == GET_MODE_SIZE (mode)
&& SUBREG_BYTE (op1) == 0 && SUBREG_BYTE (op1) == 0
@ -25972,9 +25972,9 @@ memory_address_length (rtx addr, bool lea)
index = parts.index; index = parts.index;
disp = parts.disp; disp = parts.disp;
if (base && GET_CODE (base) == SUBREG) if (base && SUBREG_P (base))
base = SUBREG_REG (base); base = SUBREG_REG (base);
if (index && GET_CODE (index) == SUBREG) if (index && SUBREG_P (index))
index = SUBREG_REG (index); index = SUBREG_REG (index);
gcc_assert (base == NULL_RTX || REG_P (base)); gcc_assert (base == NULL_RTX || REG_P (base));
@ -41617,7 +41617,7 @@ ix86_secondary_reload (bool in_p, rtx x, reg_class_t rclass,
else else
regno = -1; regno = -1;
if (regno >= FIRST_PSEUDO_REGISTER || GET_CODE (x) == SUBREG) if (regno >= FIRST_PSEUDO_REGISTER || SUBREG_P (x))
regno = true_regnum (x); regno = true_regnum (x);
/* Return Q_REGS if the operand is in memory. */ /* Return Q_REGS if the operand is in memory. */
@ -42404,7 +42404,7 @@ ix86_rtx_costs (rtx x, machine_mode mode, int outer_code_i, int opno,
{ {
if (CONST_INT_P (XEXP (x, 1))) if (CONST_INT_P (XEXP (x, 1)))
*total = cost->shift_const; *total = cost->shift_const;
else if (GET_CODE (XEXP (x, 1)) == SUBREG else if (SUBREG_P (XEXP (x, 1))
&& GET_CODE (XEXP (XEXP (x, 1), 0)) == AND) && GET_CODE (XEXP (XEXP (x, 1), 0)) == AND)
{ {
/* Return the cost after shift-and truncation. */ /* Return the cost after shift-and truncation. */
@ -50512,7 +50512,7 @@ ix86_expand_pextr (rtx *operands)
unsigned int size = INTVAL (operands[2]); unsigned int size = INTVAL (operands[2]);
unsigned int pos = INTVAL (operands[3]); unsigned int pos = INTVAL (operands[3]);
if (GET_CODE (dst) == SUBREG) if (SUBREG_P (dst))
{ {
/* Reject non-lowpart subregs. */ /* Reject non-lowpart subregs. */
if (SUBREG_BYTE (dst) > 0) if (SUBREG_BYTE (dst) > 0)
@ -50520,7 +50520,7 @@ ix86_expand_pextr (rtx *operands)
dst = SUBREG_REG (dst); dst = SUBREG_REG (dst);
} }
if (GET_CODE (src) == SUBREG) if (SUBREG_P (src))
{ {
pos += SUBREG_BYTE (src) * BITS_PER_UNIT; pos += SUBREG_BYTE (src) * BITS_PER_UNIT;
src = SUBREG_REG (src); src = SUBREG_REG (src);
@ -50615,7 +50615,7 @@ ix86_expand_pinsr (rtx *operands)
unsigned int size = INTVAL (operands[1]); unsigned int size = INTVAL (operands[1]);
unsigned int pos = INTVAL (operands[2]); unsigned int pos = INTVAL (operands[2]);
if (GET_CODE (dst) == SUBREG) if (SUBREG_P (dst))
{ {
pos += SUBREG_BYTE (dst) * BITS_PER_UNIT; pos += SUBREG_BYTE (dst) * BITS_PER_UNIT;
dst = SUBREG_REG (dst); dst = SUBREG_REG (dst);
@ -50675,7 +50675,7 @@ ix86_expand_pinsr (rtx *operands)
if (pos & (size-1)) if (pos & (size-1))
return false; return false;
if (GET_CODE (src) == SUBREG) if (SUBREG_P (src))
{ {
unsigned int srcpos = SUBREG_BYTE (src); unsigned int srcpos = SUBREG_BYTE (src);

4
gcc/config/i386/i386.md
View File

@ -2643,7 +2643,7 @@
{ {
if (TARGET_PARTIAL_REG_STALL && optimize_function_for_speed_p (cfun)) if (TARGET_PARTIAL_REG_STALL && optimize_function_for_speed_p (cfun))
FAIL; FAIL;
if (GET_CODE (operands[0]) == SUBREG if (SUBREG_P (operands[0])
&& GET_MODE_CLASS (GET_MODE (SUBREG_REG (operands[0]))) != MODE_INT) && GET_MODE_CLASS (GET_MODE (SUBREG_REG (operands[0]))) != MODE_INT)
FAIL; FAIL;
/* Don't generate memory->memory moves, go through a register */ /* Don't generate memory->memory moves, go through a register */
@ -7740,7 +7740,7 @@
val = adjust_address (val, mode, 0); val = adjust_address (val, mode, 0);
} }
} }
else if (GET_CODE (val) == SUBREG else if (SUBREG_P (val)
&& (submode = GET_MODE (SUBREG_REG (val)), && (submode = GET_MODE (SUBREG_REG (val)),
GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (submode)) GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (submode))
&& pos + len <= GET_MODE_BITSIZE (submode) && pos + len <= GET_MODE_BITSIZE (submode)

12
gcc/config/i386/predicates.md
View File

@ -101,7 +101,7 @@
if ((!TARGET_64BIT || GET_MODE (op) != DImode) if ((!TARGET_64BIT || GET_MODE (op) != DImode)
&& GET_MODE (op) != SImode && GET_MODE (op) != HImode) && GET_MODE (op) != SImode && GET_MODE (op) != HImode)
return false; return false;
if (GET_CODE (op) == SUBREG) if (SUBREG_P (op))
op = SUBREG_REG (op); op = SUBREG_REG (op);
/* Be careful to accept only registers having upper parts. */ /* Be careful to accept only registers having upper parts. */
@ -537,7 +537,7 @@
(define_predicate "call_register_no_elim_operand" (define_predicate "call_register_no_elim_operand"
(match_operand 0 "register_operand") (match_operand 0 "register_operand")
{ {
if (GET_CODE (op) == SUBREG) if (SUBREG_P (op))
op = SUBREG_REG (op); op = SUBREG_REG (op);
if (!TARGET_64BIT && op == stack_pointer_rtx) if (!TARGET_64BIT && op == stack_pointer_rtx)
@ -551,7 +551,7 @@
(define_predicate "register_no_elim_operand" (define_predicate "register_no_elim_operand"
(match_operand 0 "register_operand") (match_operand 0 "register_operand")
{ {
if (GET_CODE (op) == SUBREG) if (SUBREG_P (op))
op = SUBREG_REG (op); op = SUBREG_REG (op);
return !(op == arg_pointer_rtx return !(op == arg_pointer_rtx
|| op == frame_pointer_rtx || op == frame_pointer_rtx
@ -564,7 +564,7 @@
(define_predicate "index_register_operand" (define_predicate "index_register_operand"
(match_operand 0 "register_operand") (match_operand 0 "register_operand")
{ {
if (GET_CODE (op) == SUBREG) if (SUBREG_P (op))
op = SUBREG_REG (op); op = SUBREG_REG (op);
if (reload_completed) if (reload_completed)
return REG_OK_FOR_INDEX_STRICT_P (op); return REG_OK_FOR_INDEX_STRICT_P (op);
@ -1126,9 +1126,9 @@
ok = ix86_decompose_address (op, &parts); ok = ix86_decompose_address (op, &parts);
gcc_assert (ok); gcc_assert (ok);
if (parts.base && GET_CODE (parts.base) == SUBREG) if (parts.base && SUBREG_P (parts.base))
parts.base = SUBREG_REG (parts.base); parts.base = SUBREG_REG (parts.base);
if (parts.index && GET_CODE (parts.index) == SUBREG) if (parts.index && SUBREG_P (parts.index))
parts.index = SUBREG_REG (parts.index); parts.index = SUBREG_REG (parts.index);
/* Look for some component that isn't known to be aligned. */ /* Look for some component that isn't known to be aligned. */

2
gcc/config/i386/sse.md
View File

@ -12971,7 +12971,7 @@
[(set (match_operand:SWI48x 0 "nonimmediate_operand") [(set (match_operand:SWI48x 0 "nonimmediate_operand")
(match_operand:SWI48x 1 "register_operand"))] (match_operand:SWI48x 1 "register_operand"))]
"can_create_pseudo_p () "can_create_pseudo_p ()
&& GET_CODE (operands[1]) == SUBREG && SUBREG_P (operands[1])
&& REG_P (SUBREG_REG (operands[1])) && REG_P (SUBREG_REG (operands[1]))
&& (GET_MODE_CLASS (GET_MODE (SUBREG_REG (operands[1]))) == MODE_VECTOR_INT && (GET_MODE_CLASS (GET_MODE (SUBREG_REG (operands[1]))) == MODE_VECTOR_INT
|| (GET_MODE_CLASS (GET_MODE (SUBREG_REG (operands[1]))) || (GET_MODE_CLASS (GET_MODE (SUBREG_REG (operands[1])))