mirror of git://gcc.gnu.org/git/gcc.git
re PR target/77403 (assemble failure of vinserti64x4 with -masm=intel)
PR target/77403 * config/i386/sse.md (vec_set_lo_<mode><mask_name>): Fix assembler template for intel asm dialect. (vec_set_hi_<mode><mask_name>): Ditto. testsuite/ChangeLog: PR target/77403 * gcc.target/i386/pr77403.c: New test. From-SVN: r239834
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@ -1,3 +1,10 @@
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2016-08-29 Uros Bizjak <ubizjak@gmail.com>
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PR target/77403
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* config/i386/sse.md (vec_set_lo_<mode><mask_name>): Fix assembler
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template for intel asm dialect.
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(vec_set_hi_<mode><mask_name>): Ditto.
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2016-08-29 David Malcolm <dmalcolm@redhat.com>
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* selftest.h (selftest::fail): Add ATTRIBUTE_NORETURN.
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@ -220,7 +227,8 @@
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(ipa_read_jump_function): Add support for reading streamed ipa_bits.
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(write_ipcp_transformation_info): Add streaming for ipa_bits
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summary for ltrans.
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(read_ipcp_transfomration_info): Add support for reading streamed ipa_bits.
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(read_ipcp_transfomration_info): Add support for reading streamed
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ipa_bits.
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(ipcp_update_bits): New function.
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(ipcp_transform_function): Call ipcp_update_bits.
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@ -393,7 +401,7 @@
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* statistics.c (statistics_counter_event): Robustify against
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NULL current_pass.
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2016-08-23 Venkataramanan Kumar
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2016-08-23 Venkataramanan Kumar <venkataramanan.kumar@amd.com>
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* config/i386/i386.c (processor_alias_table): Enable PTA_PRFCHW
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for targets amdfam10 and barcelona.
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@ -12334,7 +12334,7 @@
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(const_int 12) (const_int 13)
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(const_int 14) (const_int 15)]))))]
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"TARGET_AVX512DQ"
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"vinsert<shuffletype>32x8\t{$0x0, %2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2, $0x0}"
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"vinsert<shuffletype>32x8\t{$0x0, %2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2, 0x0}"
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[(set_attr "type" "sselog")
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(set_attr "length_immediate" "1")
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(set_attr "prefix" "evex")
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@ -12351,7 +12351,7 @@
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(const_int 6) (const_int 7)]))
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(match_operand:<ssehalfvecmode> 2 "nonimmediate_operand" "vm")))]
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"TARGET_AVX512DQ"
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"vinsert<shuffletype>32x8\t{$0x1, %2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2, $0x1}"
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"vinsert<shuffletype>32x8\t{$0x1, %2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2, 0x1}"
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[(set_attr "type" "sselog")
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(set_attr "length_immediate" "1")
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(set_attr "prefix" "evex")
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@ -12366,7 +12366,7 @@
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(parallel [(const_int 4) (const_int 5)
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(const_int 6) (const_int 7)]))))]
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"TARGET_AVX512F"
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"vinsert<shuffletype>64x4\t{$0x0, %2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2, $0x0}"
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"vinsert<shuffletype>64x4\t{$0x0, %2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2, 0x0}"
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[(set_attr "type" "sselog")
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(set_attr "length_immediate" "1")
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(set_attr "prefix" "evex")
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@ -1,3 +1,8 @@
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2016-08-29 Uros Bizjak <ubizjak@gmail.com>
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PR target/77403
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* gcc.target/i386/pr77403.c: New test.
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2016-08-29 Marek Polacek <polacek@redhat.com>
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PR c/77292
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@ -0,0 +1,15 @@
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/* { dg-do assemble } */
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/* { dg-require-effective-target int128 } */
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/* { dg-require-effective-target avx512f } */
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/* { dg-require-effective-target masm_intel } */
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/* { dg-options "-O -mavx512f -masm=intel" } */
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typedef __int128 V __attribute__((vector_size(64)));
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V v;
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void
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foo()
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{
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v ^= (V){1};
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}
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