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microblaze.c: Add microblaze_asm_output_mi_thunk and define TARGET_ASM_OUTPUT_MI_THUNK and...
* config/microblaze/microblaze.c: Add microblaze_asm_output_mi_thunk and define TARGET_ASM_OUTPUT_MI_THUNK and TARGET_ASM_CAN_OUTPUT_MI_THUNK. From-SVN: r201185
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@ -1,3 +1,9 @@
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2013-07-23 David Holsgrove <david.holsgrove@xilinx.com>
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* config/microblaze/microblaze.c: Add microblaze_asm_output_mi_thunk
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and define TARGET_ASM_OUTPUT_MI_THUNK and
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TARGET_ASM_CAN_OUTPUT_MI_THUNK.
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2013-07-23 Eric Botcazou <ebotcazou@adacore.com>
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* doc/invoke.texi (SPARC Options): Document new leon3 processor value.
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@ -70,3 +70,8 @@
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"Double word operand."
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(and (match_code "mem")
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(match_test "double_memory_operand (op, GET_MODE (op))")))
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(define_memory_constraint "Q"
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"Memory operand which is a single register."
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(and (match_code "mem")
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(match_test "GET_CODE ( XEXP (op, 0)) == REG")))
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@ -2118,6 +2118,7 @@ microblaze_initial_elimination_offset (int from, int to)
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't' print 't' for EQ, 'f' for NE
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'm' Print 1<<operand.
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'i' Print 'i' if MEM operand has immediate value
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'y' Print 'y' if MEM operand is single register
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'o' Print operand address+4
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'?' Print 'd' if we use a branch with delay slot instead of normal branch.
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'h' Print high word of const_double (int or float) value as hex
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@ -2288,6 +2289,15 @@ print_operand (FILE * file, rtx op, int letter)
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rtx op4 = adjust_address (op, GET_MODE (op), 4);
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output_address (XEXP (op4, 0));
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}
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else if (letter == 'y')
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{
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rtx mem_reg = XEXP (op, 0);
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if (GET_CODE (mem_reg) == REG)
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{
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register int regnum = REGNO (mem_reg);
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fprintf (file, "%s", reg_names[regnum]);
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}
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}
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else
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output_address (XEXP (op, 0));
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@ -2221,3 +2221,5 @@
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[(set_attr "type" "arith")
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(set_attr "mode" "SI")
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(set_attr "length" "4")])
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(include "sync.md")
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@ -0,0 +1,43 @@
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;; Machine description for Xilinx MicroBlaze synchronization instructions.
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;; Copyright (C) 2011-2013 Free Software Foundation, Inc.
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published
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;; by the Free Software Foundation; either version 3, or (at your
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;; option) any later version.
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;;
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;; GCC is distributed in the hope that it will be useful, but WITHOUT
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;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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;; License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; <http://www.gnu.org/licenses/>.
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(define_insn "atomic_compare_and_swapsi"
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[(match_operand:SI 0 "register_operand" "=&d") ;; bool output
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(match_operand:SI 1 "register_operand" "=&d") ;; val output
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(match_operand:SI 2 "nonimmediate_operand" "+Q") ;; memory
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(match_operand:SI 3 "register_operand" "d") ;; expected value
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(match_operand:SI 4 "register_operand" "d") ;; desired value
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(match_operand:SI 5 "const_int_operand" "") ;; is_weak
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(match_operand:SI 6 "const_int_operand" "") ;; mod_s
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(match_operand:SI 7 "const_int_operand" "") ;; mod_f
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(clobber (match_scratch:SI 8 "=&d"))]
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""
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{
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output_asm_insn ("addc \tr0,r0,r0", operands);
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output_asm_insn ("lwx \t%1,%y2,r0", operands);
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output_asm_insn ("addic\t%8,r0,0", operands);
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output_asm_insn ("bnei \t%8,.-8", operands);
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output_asm_insn ("cmp \t%0,%1,%3", operands);
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output_asm_insn ("bnei \t%0,.+16", operands);
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output_asm_insn ("swx \t%4,%y2,r0", operands);
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output_asm_insn ("addic\t%8,r0,0", operands);
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output_asm_insn ("bnei \t%8,.-28", operands);
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return "";
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}
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)
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