mirror of git://gcc.gnu.org/git/gcc.git
avr.md: Tidy up empty "".
* config/avr/avr.md: Tidy up empty "". Fix C code indentation. * config/avr/avr-fixed.md: Ditto. From-SVN: r191436
This commit is contained in:
Georg-Johann Lay
Georg-Johann Lay
parent
d4c059d582
commit
487e359c28
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@ -1,3 +1,8 @@
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2012-09-18 Georg-Johann Lay <avr@gjlay.de>
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* config/avr/avr.md: Tidy up empty "". Fix C code indentation.
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* config/avr/avr-fixed.md: Ditto.
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2012-09-18 Maciej W. Rozycki <macro@codesourcery.com>
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* config/rs6000/rs6000.c (print_operand) <'c'>: Remove.
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@ -22,12 +22,12 @@
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;; along with GCC; see the file COPYING3. If not see
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;; <http://www.gnu.org/licenses/>.
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(define_mode_iterator ALL1Q [(QQ "") (UQQ "")])
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(define_mode_iterator ALL2Q [(HQ "") (UHQ "")])
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(define_mode_iterator ALL2A [(HA "") (UHA "")])
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(define_mode_iterator ALL2QA [(HQ "") (UHQ "")
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(HA "") (UHA "")])
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(define_mode_iterator ALL4A [(SA "") (USA "")])
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(define_mode_iterator ALL1Q [QQ UQQ])
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(define_mode_iterator ALL2Q [HQ UHQ])
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(define_mode_iterator ALL2A [HA UHA])
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(define_mode_iterator ALL2QA [HQ UHQ
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HA UHA])
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(define_mode_iterator ALL4A [SA USA])
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(define_mode_iterator ALL2S [HQ HA])
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(define_mode_iterator ALL4S [SA SQ])
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@ -38,22 +38,22 @@
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;;; Conversions
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(define_mode_iterator FIXED_A
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[(QQ "") (UQQ "")
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(HQ "") (UHQ "") (HA "") (UHA "")
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(SQ "") (USQ "") (SA "") (USA "")
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(DQ "") (UDQ "") (DA "") (UDA "")
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(TA "") (UTA "")
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(QI "") (HI "") (SI "") (DI "")])
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[QQ UQQ
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HQ UHQ HA UHA
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SQ USQ SA USA
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DQ UDQ DA UDA
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TA UTA
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QI HI SI DI])
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;; Same so that be can build cross products
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(define_mode_iterator FIXED_B
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[(QQ "") (UQQ "")
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(HQ "") (UHQ "") (HA "") (UHA "")
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(SQ "") (USQ "") (SA "") (USA "")
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(DQ "") (UDQ "") (DA "") (UDA "")
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(TA "") (UTA "")
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(QI "") (HI "") (SI "") (DI "")])
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[QQ UQQ
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HQ UHQ HA UHA
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SQ USQ SA USA
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DQ UDQ DA UDA
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TA UTA
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QI HI SI DI])
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(define_insn "fract<FIXED_B:mode><FIXED_A:mode>2"
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[(set (match_operand:FIXED_A 0 "register_operand" "=r")
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@ -220,26 +220,26 @@
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;; Define mode iterators
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(define_mode_iterator QIHI [(QI "") (HI "")])
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(define_mode_iterator QIHI2 [(QI "") (HI "")])
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(define_mode_iterator QISI [(QI "") (HI "") (PSI "") (SI "")])
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(define_mode_iterator QIDI [(QI "") (HI "") (PSI "") (SI "") (DI "")])
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(define_mode_iterator HISI [(HI "") (PSI "") (SI "")])
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(define_mode_iterator QIHI [QI HI])
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(define_mode_iterator QIHI2 [QI HI])
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(define_mode_iterator QISI [QI HI PSI SI])
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(define_mode_iterator QIDI [QI HI PSI SI DI])
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(define_mode_iterator HISI [HI PSI SI])
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(define_mode_iterator ALL1 [(QI "") (QQ "") (UQQ "")])
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(define_mode_iterator ALL2 [(HI "") (HQ "") (UHQ "") (HA "") (UHA "")])
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(define_mode_iterator ALL4 [(SI "") (SQ "") (USQ "") (SA "") (USA "")])
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(define_mode_iterator ALL1 [QI QQ UQQ])
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(define_mode_iterator ALL2 [HI HQ UHQ HA UHA])
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(define_mode_iterator ALL4 [SI SQ USQ SA USA])
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;; All supported move-modes
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(define_mode_iterator MOVMODE [(QI "") (HI "") (SI "") (SF "") (PSI "")
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(QQ "") (UQQ "")
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(HQ "") (UHQ "") (HA "") (UHA "")
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(SQ "") (USQ "") (SA "") (USA "")])
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(define_mode_iterator MOVMODE [QI QQ UQQ
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HI HQ UHQ HA UHA
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SI SQ USQ SA USA
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SF PSI])
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;; Supported ordered modes that are 2, 3, 4 bytes wide
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(define_mode_iterator ORDERED234 [(HI "") (SI "") (PSI "")
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(HQ "") (UHQ "") (HA "") (UHA "")
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(SQ "") (USQ "") (SA "") (USA "")])
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(define_mode_iterator ORDERED234 [HI SI PSI
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HQ UHQ HA UHA
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SQ USQ SA USA])
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;; Define code iterators
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;; Define two incarnations so that we can build the cross product.
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@ -305,8 +305,8 @@
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gen_rtx_PLUS (Pmode, hard_frame_pointer_rtx,
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gen_int_mode (STARTING_FRAME_OFFSET,
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Pmode)));
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/* This might change the hard frame pointer in ways that aren't
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apparent to early optimization passes, so force a clobber. */
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/* ; This might change the hard frame pointer in ways that aren't
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; apparent to early optimization passes, so force a clobber. */
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emit_clobber (hard_frame_pointer_rtx);
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DONE;
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})
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@ -321,25 +321,25 @@
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(use (match_operand 2 "general_operand"))
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(use (match_operand 3 "general_operand"))]
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""
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{
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rtx r_label = copy_to_reg (operands[1]);
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rtx r_fp = operands[3];
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rtx r_sp = operands[2];
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{
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rtx r_label = copy_to_reg (operands[1]);
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rtx r_fp = operands[3];
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rtx r_sp = operands[2];
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emit_clobber (gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode)));
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emit_clobber (gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode)));
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emit_clobber (gen_rtx_MEM (BLKmode, hard_frame_pointer_rtx));
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emit_clobber (gen_rtx_MEM (BLKmode, hard_frame_pointer_rtx));
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emit_move_insn (hard_frame_pointer_rtx, r_fp);
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emit_stack_restore (SAVE_NONLOCAL, r_sp);
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emit_move_insn (hard_frame_pointer_rtx, r_fp);
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emit_stack_restore (SAVE_NONLOCAL, r_sp);
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emit_use (hard_frame_pointer_rtx);
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emit_use (stack_pointer_rtx);
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emit_use (hard_frame_pointer_rtx);
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emit_use (stack_pointer_rtx);
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emit_indirect_jump (r_label);
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emit_indirect_jump (r_label);
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DONE;
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})
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DONE;
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})
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;; "pushqi1"
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;; "pushqq1" "pushuqq1"
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@ -353,44 +353,42 @@
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[(set_attr "length" "1,1")])
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;; All modes for a multi-byte push. We must include complex modes here too,
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;; lest emit_single_push_insn "helpfully " create the auto-inc itself.
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;; lest emit_single_push_insn "helpfully" create the auto-inc itself.
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(define_mode_iterator MPUSH
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[(CQI "")
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(HI "") (CHI "")
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(PSI "")
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(SI "") (CSI "")
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(DI "") (CDI "")
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(SF "") (SC "")
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(HA "") (UHA "") (HQ "") (UHQ "")
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(SA "") (USA "") (SQ "") (USQ "")
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(DA "") (UDA "") (DQ "") (UDQ "")
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(TA "") (UTA "")])
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[CQI
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HI CHI HA UHA HQ UHQ
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SI CSI SA USA SQ USQ
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DI CDI DA UDA DQ UDQ
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TA UTA
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SF SC
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PSI])
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(define_expand "push<mode>1"
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[(match_operand:MPUSH 0 "" "")]
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""
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{
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int i;
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for (i = GET_MODE_SIZE (<MODE>mode) - 1; i >= 0; --i)
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{
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rtx part = simplify_gen_subreg (QImode, operands[0], <MODE>mode, i);
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if (part != const0_rtx)
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part = force_reg (QImode, part);
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emit_insn (gen_pushqi1 (part));
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}
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DONE;
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})
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{
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int i;
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for (i = GET_MODE_SIZE (<MODE>mode) - 1; i >= 0; --i)
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{
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rtx part = simplify_gen_subreg (QImode, operands[0], <MODE>mode, i);
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if (part != const0_rtx)
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part = force_reg (QImode, part);
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emit_insn (gen_pushqi1 (part));
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}
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DONE;
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})
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;; Notice a special-case when adding N to SP where N results in a
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;; zero REG_ARGS_SIZE. This is equivalent to a move from FP.
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(define_split
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[(set (reg:HI REG_SP) (match_operand:HI 0 "register_operand" ""))]
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[(set (reg:HI REG_SP)
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(match_operand:HI 0 "register_operand" ""))]
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"reload_completed
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&& frame_pointer_needed
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&& !cfun->calls_alloca
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&& find_reg_note (insn, REG_ARGS_SIZE, const0_rtx)"
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[(set (reg:HI REG_SP) (reg:HI REG_Y))]
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"")
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[(set (reg:HI REG_SP)
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(reg:HI REG_Y))])
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;;========================================================================
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;; Move stuff around
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@ -775,9 +773,9 @@
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(match_operand:ALL1 1 "even_register_operand" ""))
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(set (match_operand:ALL1 2 "odd_register_operand" "")
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(match_operand:ALL1 3 "odd_register_operand" ""))]
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"(AVR_HAVE_MOVW
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&& REGNO (operands[0]) == REGNO (operands[2]) - 1
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&& REGNO (operands[1]) == REGNO (operands[3]) - 1)"
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"AVR_HAVE_MOVW
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&& REGNO (operands[0]) == REGNO (operands[2]) - 1
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&& REGNO (operands[1]) == REGNO (operands[3]) - 1"
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[(set (match_dup 4)
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(match_dup 5))]
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{
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@ -790,9 +788,9 @@
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(match_operand:ALL1 1 "odd_register_operand" ""))
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(set (match_operand:ALL1 2 "even_register_operand" "")
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(match_operand:ALL1 3 "even_register_operand" ""))]
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"(AVR_HAVE_MOVW
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&& REGNO (operands[2]) == REGNO (operands[0]) - 1
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&& REGNO (operands[3]) == REGNO (operands[1]) - 1)"
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"AVR_HAVE_MOVW
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&& REGNO (operands[2]) == REGNO (operands[0]) - 1
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&& REGNO (operands[3]) == REGNO (operands[1]) - 1"
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[(set (match_dup 4)
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(match_dup 5))]
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{
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@ -812,8 +810,7 @@
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&& operands[1] != constm1_rtx"
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[(parallel [(set (match_dup 0)
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(match_dup 1))
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(clobber (match_dup 2))])]
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"")
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(clobber (match_dup 2))])])
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;; '*' because it is not used in rtl generation.
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(define_insn "*reload_inpsi"
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@ -1481,9 +1478,7 @@
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(set (reg:QI 22) (match_operand:QI 2 "register_operand" ""))
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(parallel [(set (reg:QI 24) (mult:QI (reg:QI 24) (reg:QI 22)))
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(clobber (reg:QI 22))])
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(set (match_operand:QI 0 "register_operand" "") (reg:QI 24))]
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""
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"")
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(set (match_operand:QI 0 "register_operand" "") (reg:QI 24))])
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(define_insn "*mulqi3_call"
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[(set (reg:QI 24) (mult:QI (reg:QI 24) (reg:QI 22)))
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@ -1684,8 +1679,7 @@
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(set (match_dup 0)
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(plus:QI (mult:QI (match_dup 1)
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(match_dup 4))
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(match_dup 3)))]
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"")
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(match_dup 3)))])
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(define_insn_and_split "*msubqi4.const"
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[(set (match_operand:QI 0 "register_operand" "=r")
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@ -1702,8 +1696,7 @@
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(set (match_dup 0)
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(minus:QI (match_dup 3)
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(mult:QI (match_dup 1)
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(match_dup 4))))]
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"")
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(match_dup 4))))])
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;******************************************************************************
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@ -2213,9 +2206,7 @@
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(parallel [(set (reg:HI 24) (mult:HI (reg:HI 24) (reg:HI 22)))
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(clobber (reg:HI 22))
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(clobber (reg:QI 21))])
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(set (match_operand:HI 0 "register_operand" "") (reg:HI 24))]
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""
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"")
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(set (match_operand:HI 0 "register_operand" "") (reg:HI 24))])
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(define_insn "*mulhi3_call"
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[(set (reg:HI 24) (mult:HI (reg:HI 24) (reg:HI 22)))
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@ -2389,8 +2380,7 @@
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(mult:SI (not:SI (zero_extend:SI (not:HI (reg:HI 26))))
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(reg:SI 18)))
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(set (match_dup 0)
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(reg:SI 22))]
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"")
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(reg:SI 22))])
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;; "mulhisi3"
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;; "umulhisi3"
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@ -2400,8 +2390,7 @@
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(any_extend:SI (match_operand:HI 2 "register_operand" ""))))
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(clobber (reg:HI 26))
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(clobber (reg:DI 18))])]
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"AVR_HAVE_MUL"
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"")
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"AVR_HAVE_MUL")
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(define_expand "usmulhisi3"
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[(parallel [(set (match_operand:SI 0 "register_operand" "")
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@ -2409,8 +2398,7 @@
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(sign_extend:SI (match_operand:HI 2 "register_operand" ""))))
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(clobber (reg:HI 26))
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(clobber (reg:DI 18))])]
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"AVR_HAVE_MUL"
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"")
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"AVR_HAVE_MUL")
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;; "*uumulqihisi3" "*uumulhiqisi3" "*uumulhihisi3" "*uumulqiqisi3"
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;; "*usmulqihisi3" "*usmulhiqisi3" "*usmulhihisi3" "*usmulqiqisi3"
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@ -2482,8 +2470,7 @@
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(clobber (reg:HI 22))])
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(set (match_operand:HI 0 "register_operand" "")
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(reg:HI 24))]
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"AVR_HAVE_MUL"
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"")
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"AVR_HAVE_MUL")
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(define_insn "*mulsi3_call"
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@ -2577,8 +2564,7 @@
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(clobber (reg:QI 22))
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(clobber (reg:QI 23))])
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(set (match_dup 0) (reg:QI 24))
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(set (match_dup 3) (reg:QI 25))]
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"")
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(set (match_dup 3) (reg:QI 25))])
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(define_insn "*divmodqi4_call"
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[(set (reg:QI 24) (div:QI (reg:QI 24) (reg:QI 22)))
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@ -2609,8 +2595,7 @@
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(set (reg:QI 25) (umod:QI (reg:QI 24) (reg:QI 22)))
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(clobber (reg:QI 23))])
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(set (match_dup 0) (reg:QI 24))
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(set (match_dup 3) (reg:QI 25))]
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"")
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(set (match_dup 3) (reg:QI 25))])
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(define_insn "*udivmodqi4_call"
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[(set (reg:QI 24) (udiv:QI (reg:QI 24) (reg:QI 22)))
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@ -2641,8 +2626,7 @@
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(clobber (reg:HI 26))
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(clobber (reg:QI 21))])
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(set (match_dup 0) (reg:HI 22))
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(set (match_dup 3) (reg:HI 24))]
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"")
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(set (match_dup 3) (reg:HI 24))])
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(define_insn "*divmodhi4_call"
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[(set (reg:HI 22) (div:HI (reg:HI 24) (reg:HI 22)))
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@ -2674,8 +2658,7 @@
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(clobber (reg:HI 26))
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(clobber (reg:QI 21))])
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(set (match_dup 0) (reg:HI 22))
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(set (match_dup 3) (reg:HI 24))]
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"")
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(set (match_dup 3) (reg:HI 24))])
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(define_insn "*udivmodhi4_call"
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[(set (reg:HI 22) (udiv:HI (reg:HI 24) (reg:HI 22)))
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@ -2907,8 +2890,7 @@
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(clobber (reg:HI 26))
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(clobber (reg:HI 30))])
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(set (match_dup 0) (reg:SI 18))
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(set (match_dup 3) (reg:SI 22))]
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"")
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(set (match_dup 3) (reg:SI 22))])
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(define_insn "*divmodsi4_call"
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[(set (reg:SI 18) (div:SI (reg:SI 22) (reg:SI 18)))
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@ -2940,8 +2922,7 @@
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(clobber (reg:HI 26))
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(clobber (reg:HI 30))])
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(set (match_dup 0) (reg:SI 18))
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(set (match_dup 3) (reg:SI 22))]
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"")
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(set (match_dup 3) (reg:SI 22))])
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(define_insn "*udivmodsi4_call"
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[(set (reg:SI 18) (udiv:SI (reg:SI 22) (reg:SI 18)))
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@ -3609,8 +3590,7 @@
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[(parallel [(set (match_dup 0)
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||||
(ashift:ALL4 (match_dup 1)
|
||||
(match_dup 2)))
|
||||
(clobber (match_dup 3))])]
|
||||
"")
|
||||
(clobber (match_dup 3))])])
|
||||
|
||||
;; "*ashlsi3_const"
|
||||
;; "*ashlsq3_const" "*ashlusq3_const"
|
||||
|
|
@ -4351,7 +4331,7 @@
|
|||
[(set (cc0)
|
||||
(compare (neg:QI (match_operand:QI 0 "register_operand" "r"))
|
||||
(const_int 0)))]
|
||||
"(!flag_wrapv && !flag_trapv && flag_strict_overflow)"
|
||||
"!flag_wrapv && !flag_trapv && flag_strict_overflow"
|
||||
"cp __zero_reg__,%0"
|
||||
[(set_attr "cc" "compare")
|
||||
(set_attr "length" "1")])
|
||||
|
|
@ -4369,7 +4349,7 @@
|
|||
[(set (cc0)
|
||||
(compare (neg:HI (match_operand:HI 0 "register_operand" "r"))
|
||||
(const_int 0)))]
|
||||
"(!flag_wrapv && !flag_trapv && flag_strict_overflow)"
|
||||
"!flag_wrapv && !flag_trapv && flag_strict_overflow"
|
||||
"cp __zero_reg__,%A0
|
||||
cpc __zero_reg__,%B0"
|
||||
[(set_attr "cc" "compare")
|
||||
|
|
@ -4411,7 +4391,7 @@
|
|||
[(set (cc0)
|
||||
(compare (neg:SI (match_operand:SI 0 "register_operand" "r"))
|
||||
(const_int 0)))]
|
||||
"(!flag_wrapv && !flag_trapv && flag_strict_overflow)"
|
||||
"!flag_wrapv && !flag_trapv && flag_strict_overflow"
|
||||
"cp __zero_reg__,%A0
|
||||
cpc __zero_reg__,%B0
|
||||
cpc __zero_reg__,%C0
|
||||
|
|
@ -4654,8 +4634,7 @@
|
|||
(const_int 7))
|
||||
(const_int 0))
|
||||
(label_ref (match_dup 1))
|
||||
(pc)))]
|
||||
"")
|
||||
(pc)))])
|
||||
|
||||
(define_peephole2
|
||||
[(set (cc0) (compare (match_operand:QI 0 "register_operand" "")
|
||||
|
|
@ -4669,8 +4648,7 @@
|
|||
(const_int 7))
|
||||
(const_int 0))
|
||||
(label_ref (match_dup 1))
|
||||
(pc)))]
|
||||
"")
|
||||
(pc)))])
|
||||
|
||||
(define_peephole2
|
||||
[(parallel [(set (cc0) (compare (match_operand:HI 0 "register_operand" "")
|
||||
|
|
@ -4683,8 +4661,7 @@
|
|||
[(set (pc) (if_then_else (eq (and:HI (match_dup 0) (const_int -32768))
|
||||
(const_int 0))
|
||||
(label_ref (match_dup 1))
|
||||
(pc)))]
|
||||
"")
|
||||
(pc)))])
|
||||
|
||||
(define_peephole2
|
||||
[(parallel [(set (cc0) (compare (match_operand:HI 0 "register_operand" "")
|
||||
|
|
@ -4697,8 +4674,7 @@
|
|||
[(set (pc) (if_then_else (ne (and:HI (match_dup 0) (const_int -32768))
|
||||
(const_int 0))
|
||||
(label_ref (match_dup 1))
|
||||
(pc)))]
|
||||
"")
|
||||
(pc)))])
|
||||
|
||||
(define_peephole2
|
||||
[(parallel [(set (cc0) (compare (match_operand:SI 0 "register_operand" "")
|
||||
|
|
@ -4712,7 +4688,7 @@
|
|||
(const_int 0))
|
||||
(label_ref (match_dup 1))
|
||||
(pc)))]
|
||||
"operands[2] = GEN_INT (-2147483647 - 1);")
|
||||
"operands[2] = gen_int_mode (-2147483647 - 1, SImode);")
|
||||
|
||||
(define_peephole2
|
||||
[(parallel [(set (cc0) (compare (match_operand:SI 0 "register_operand" "")
|
||||
|
|
@ -4726,7 +4702,7 @@
|
|||
(const_int 0))
|
||||
(label_ref (match_dup 1))
|
||||
(pc)))]
|
||||
"operands[2] = GEN_INT (-2147483647 - 1);")
|
||||
"operands[2] = gen_int_mode (-2147483647 - 1, SImode);")
|
||||
|
||||
;; ************************************************************************
|
||||
;; Implementation of conditional jumps here.
|
||||
|
|
@ -4840,45 +4816,37 @@
|
|||
|
||||
;; call
|
||||
|
||||
;; Operand 1 not used on the AVR.
|
||||
;; Operand 2 is 1 for tail-call, 0 otherwise.
|
||||
(define_expand "call"
|
||||
[(parallel[(call (match_operand:HI 0 "call_insn_operand" "")
|
||||
(match_operand:HI 1 "general_operand" ""))
|
||||
(use (const_int 0))])]
|
||||
;; Operand 1 not used on the AVR.
|
||||
;; Operand 2 is 1 for tail-call, 0 otherwise.
|
||||
""
|
||||
"")
|
||||
(use (const_int 0))])])
|
||||
|
||||
;; Operand 1 not used on the AVR.
|
||||
;; Operand 2 is 1 for tail-call, 0 otherwise.
|
||||
(define_expand "sibcall"
|
||||
[(parallel[(call (match_operand:HI 0 "call_insn_operand" "")
|
||||
(match_operand:HI 1 "general_operand" ""))
|
||||
(use (const_int 1))])]
|
||||
;; Operand 1 not used on the AVR.
|
||||
;; Operand 2 is 1 for tail-call, 0 otherwise.
|
||||
""
|
||||
"")
|
||||
(use (const_int 1))])])
|
||||
|
||||
;; call value
|
||||
|
||||
;; Operand 2 not used on the AVR.
|
||||
;; Operand 3 is 1 for tail-call, 0 otherwise.
|
||||
(define_expand "call_value"
|
||||
[(parallel[(set (match_operand 0 "register_operand" "")
|
||||
(call (match_operand:HI 1 "call_insn_operand" "")
|
||||
(match_operand:HI 2 "general_operand" "")))
|
||||
(use (const_int 0))])]
|
||||
;; Operand 2 not used on the AVR.
|
||||
;; Operand 3 is 1 for tail-call, 0 otherwise.
|
||||
""
|
||||
"")
|
||||
(use (const_int 0))])])
|
||||
|
||||
;; Operand 2 not used on the AVR.
|
||||
;; Operand 3 is 1 for tail-call, 0 otherwise.
|
||||
(define_expand "sibcall_value"
|
||||
[(parallel[(set (match_operand 0 "register_operand" "")
|
||||
(call (match_operand:HI 1 "call_insn_operand" "")
|
||||
(match_operand:HI 2 "general_operand" "")))
|
||||
(use (const_int 1))])]
|
||||
;; Operand 2 not used on the AVR.
|
||||
;; Operand 3 is 1 for tail-call, 0 otherwise.
|
||||
""
|
||||
"")
|
||||
(use (const_int 1))])])
|
||||
|
||||
(define_insn "call_insn"
|
||||
[(parallel[(call (mem:HI (match_operand:HI 0 "nonmemory_operand" "z,s,z,s"))
|
||||
|
|
@ -5069,11 +5037,11 @@
|
|||
(label_ref (match_operand 2 "" ""))
|
||||
(pc)))]
|
||||
""
|
||||
{
|
||||
operands[3] = operands[2];
|
||||
operands[2] = GEN_INT (7);
|
||||
return avr_out_sbxx_branch (insn, operands);
|
||||
}
|
||||
{
|
||||
operands[3] = operands[2];
|
||||
operands[2] = GEN_INT (7);
|
||||
return avr_out_sbxx_branch (insn, operands);
|
||||
}
|
||||
[(set (attr "length")
|
||||
(if_then_else (and (ge (minus (pc) (match_dup 2)) (const_int -2046))
|
||||
(le (minus (pc) (match_dup 2)) (const_int 2046)))
|
||||
|
|
@ -5117,11 +5085,11 @@
|
|||
(label_ref (match_operand 2 "" ""))
|
||||
(pc)))]
|
||||
""
|
||||
{
|
||||
operands[3] = operands[2];
|
||||
operands[2] = GEN_INT (7);
|
||||
return avr_out_sbxx_branch (insn, operands);
|
||||
}
|
||||
{
|
||||
operands[3] = operands[2];
|
||||
operands[2] = GEN_INT (7);
|
||||
return avr_out_sbxx_branch (insn, operands);
|
||||
}
|
||||
[(set (attr "length")
|
||||
(if_then_else (and (ge (minus (pc) (match_dup 2)) (const_int -2046))
|
||||
(le (minus (pc) (match_dup 2)) (const_int 2045)))
|
||||
|
|
@ -5479,29 +5447,29 @@
|
|||
|
||||
(define_insn "return_from_epilogue"
|
||||
[(return)]
|
||||
"(reload_completed
|
||||
&& cfun->machine
|
||||
&& !(cfun->machine->is_interrupt || cfun->machine->is_signal)
|
||||
&& !cfun->machine->is_naked)"
|
||||
"reload_completed
|
||||
&& cfun->machine
|
||||
&& !(cfun->machine->is_interrupt || cfun->machine->is_signal)
|
||||
&& !cfun->machine->is_naked"
|
||||
"ret"
|
||||
[(set_attr "cc" "none")
|
||||
(set_attr "length" "1")])
|
||||
|
||||
(define_insn "return_from_interrupt_epilogue"
|
||||
[(return)]
|
||||
"(reload_completed
|
||||
&& cfun->machine
|
||||
&& (cfun->machine->is_interrupt || cfun->machine->is_signal)
|
||||
&& !cfun->machine->is_naked)"
|
||||
"reload_completed
|
||||
&& cfun->machine
|
||||
&& (cfun->machine->is_interrupt || cfun->machine->is_signal)
|
||||
&& !cfun->machine->is_naked"
|
||||
"reti"
|
||||
[(set_attr "cc" "none")
|
||||
(set_attr "length" "1")])
|
||||
|
||||
(define_insn "return_from_naked_epilogue"
|
||||
[(return)]
|
||||
"(reload_completed
|
||||
&& cfun->machine
|
||||
&& cfun->machine->is_naked)"
|
||||
"reload_completed
|
||||
&& cfun->machine
|
||||
&& cfun->machine->is_naked"
|
||||
""
|
||||
[(set_attr "cc" "none")
|
||||
(set_attr "length" "0")])
|
||||
|
|
@ -5805,8 +5773,7 @@
|
|||
[(set (reg:QI 24)
|
||||
(popcount:QI (reg:QI 24)))
|
||||
(set (reg:QI 25)
|
||||
(const_int 0))]
|
||||
"")
|
||||
(const_int 0))])
|
||||
|
||||
;; Count Leading Zeros
|
||||
|
||||
|
|
@ -5817,9 +5784,7 @@
|
|||
(clz:HI (reg:HI 24)))
|
||||
(clobber (reg:QI 26))])
|
||||
(set (match_operand:HI 0 "register_operand" "")
|
||||
(reg:HI 24))]
|
||||
""
|
||||
"")
|
||||
(reg:HI 24))])
|
||||
|
||||
(define_expand "clzsi2"
|
||||
[(set (reg:SI 22)
|
||||
|
|
@ -5863,9 +5828,7 @@
|
|||
(ctz:HI (reg:HI 24)))
|
||||
(clobber (reg:QI 26))])
|
||||
(set (match_operand:HI 0 "register_operand" "")
|
||||
(reg:HI 24))]
|
||||
""
|
||||
"")
|
||||
(reg:HI 24))])
|
||||
|
||||
(define_expand "ctzsi2"
|
||||
[(set (reg:SI 22)
|
||||
|
|
@ -5911,9 +5874,7 @@
|
|||
(ffs:HI (reg:HI 24)))
|
||||
(clobber (reg:QI 26))])
|
||||
(set (match_operand:HI 0 "register_operand" "")
|
||||
(reg:HI 24))]
|
||||
""
|
||||
"")
|
||||
(reg:HI 24))])
|
||||
|
||||
(define_expand "ffssi2"
|
||||
[(set (reg:SI 22)
|
||||
|
|
@ -5970,9 +5931,7 @@
|
|||
(set (reg:SI 22)
|
||||
(bswap:SI (reg:SI 22)))
|
||||
(set (match_operand:SI 0 "register_operand" "")
|
||||
(reg:SI 22))]
|
||||
""
|
||||
"")
|
||||
(reg:SI 22))])
|
||||
|
||||
(define_insn "*bswapsi2.libgcc"
|
||||
[(set (reg:SI 22)
|
||||
|
|
@ -6275,8 +6234,7 @@
|
|||
(match_operand:QI 1 "const1_operand" "") ; width
|
||||
(match_operand:QI 2 "const_0_to_7_operand" "")) ; pos
|
||||
(match_operand:QI 3 "nonmemory_operand" ""))]
|
||||
"optimize"
|
||||
"")
|
||||
"optimize")
|
||||
|
||||
;; Insert bit $2.0 into $0.$1
|
||||
(define_insn "*insv.reg"
|
||||
|
|
@ -6341,9 +6299,7 @@
|
|||
[(set (match_operand:QI 0 "register_operand" "")
|
||||
(zero_extract:QI (match_operand:QI 1 "register_operand" "")
|
||||
(match_operand:QI 2 "const1_operand" "")
|
||||
(match_operand:QI 3 "const_0_to_7_operand" "")))]
|
||||
""
|
||||
"")
|
||||
(match_operand:QI 3 "const_0_to_7_operand" "")))])
|
||||
|
||||
(define_insn "*extzv"
|
||||
[(set (match_operand:QI 0 "register_operand" "=*d,*d,*d,*d,r")
|
||||
|
|
|
|||
Loading…
Reference in New Issue