mirror of git://gcc.gnu.org/git/gcc.git
m68k: Convert to atomic_test_and_set.
* config/m68k/m68k.c (TARGET_ATOMIC_TEST_AND_SET_TRUEVAL): New.
* config/m68k/sync.md (atomic_test_and_set): Rename from
sync_test_and_setqi and adjust the operands.
(atomic_test_and_set_1): Rename from sync_test_and_setqi_1
and unconditionally enable.
From-SVN: r183585
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5a843a13dc
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4c1fd0845e
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@ -1,3 +1,11 @@
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2012-01-27 Richard Henderson <rth@redhat.com>
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* config/m68k/m68k.c (TARGET_ATOMIC_TEST_AND_SET_TRUEVAL): New.
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* config/m68k/sync.md (atomic_test_and_set): Rename from
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sync_test_and_setqi and adjust the operands.
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(atomic_test_and_set_1): Rename from sync_test_and_setqi_1
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and unconditionally enable.
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2012-01-27 Richard Henderson <rth@redhat.com>
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2012-01-27 Richard Henderson <rth@redhat.com>
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* config/sparc/sparc.c (TARGET_ATOMIC_TEST_AND_SET_TRUEVAL): New.
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* config/sparc/sparc.c (TARGET_ATOMIC_TEST_AND_SET_TRUEVAL): New.
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@ -303,6 +303,10 @@ static void m68k_init_sync_libfuncs (void) ATTRIBUTE_UNUSED;
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#undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
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#undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
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#define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA m68k_output_addr_const_extra
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#define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA m68k_output_addr_const_extra
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/* The value stored by TAS. */
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#undef TARGET_ATOMIC_TEST_AND_SET_TRUEVAL
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#define TARGET_ATOMIC_TEST_AND_SET_TRUEVAL 128
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static const struct attribute_spec m68k_attribute_table[] =
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static const struct attribute_spec m68k_attribute_table[] =
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{
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{
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/* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
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/* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
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@ -56,25 +56,23 @@
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;; Elide the seq if operands[0] is dead.
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;; Elide the seq if operands[0] is dead.
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"cas<sz> %1,%4,%2\;seq %0")
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"cas<sz> %1,%4,%2\;seq %0")
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(define_expand "sync_test_and_setqi"
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(define_expand "atomic_test_and_set"
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[(match_operand:QI 0 "register_operand" "")
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[(match_operand:QI 0 "register_operand" "") ;; bool success output
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(match_operand:QI 1 "memory_operand" "")
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(match_operand:QI 1 "memory_operand" "") ;; memory
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(match_operand:QI 2 "general_operand" "")]
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(match_operand:SI 2 "const_int_operand" "")] ;; model
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"!TARGET_CAS"
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""
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{
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{
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if (operands[2] != const1_rtx)
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emit_insn (gen_atomic_test_and_set_1 (operands[0], operands[1]));
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FAIL;
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emit_insn (gen_sync_test_and_setqi_1 (operands[0], operands[1]));
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emit_insn (gen_negqi2 (operands[0], operands[0]));
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emit_insn (gen_negqi2 (operands[0], operands[0]));
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DONE;
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DONE;
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})
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})
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(define_insn "sync_test_and_setqi_1"
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(define_insn "atomic_test_and_set_1"
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[(set (match_operand:QI 0 "register_operand" "=d")
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[(set (match_operand:QI 0 "register_operand" "=d")
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(unspec_volatile:QI
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(unspec_volatile:QI
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[(match_operand:QI 1 "memory_operand" "+m")]
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[(match_operand:QI 1 "memory_operand" "+m")]
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UNSPECV_TAS_1))
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UNSPECV_TAS_1))
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(set (match_dup 1)
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(set (match_dup 1)
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(unspec_volatile:QI [(match_dup 1)] UNSPECV_TAS_2))]
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(unspec_volatile:QI [(match_dup 1)] UNSPECV_TAS_2))]
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"!TARGET_CAS"
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""
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"tas %1\;sne %0")
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"tas %1\;sne %0")
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