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[AArch64] Tweak sve/vcond_6.c test 

sve/vcond_6.c was effectively testing a three-input logical operation,
since the result of BINOP needed to be ANDed with the loop predicate
before loading src[i].  This patch makes it really test a binary
operation instead.  A later patch will add (and optimise) the
three-operand case.

2018-05-08  Richard Sandiford  <richard.sandiford@linaro.org>

gcc/testsuite/
	* gcc.target/aarch64/sve/vcond_6.c (LOOP): Unconditionally
	load from src[i].

From-SVN: r260028
This commit is contained in:
Richard Sandiford 2018-05-08 09:35:36 +00:00 committed by Richard Sandiford
parent 3e8f909a06
commit 4fdd8b18ec
2 changed files with 12 additions and 6 deletions
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5
gcc/testsuite/ChangeLog
View File

@ -1,3 +1,8 @@
2018-05-08 Richard Sandiford <richard.sandiford@linaro.org>
* gcc.target/aarch64/sve/vcond_6.c (LOOP): Unconditionally
load from src[i].
2018-05-08 Paolo Carlini <paolo.carlini@oracle.com> 2018-05-08 Paolo Carlini <paolo.carlini@oracle.com>
PR c++/80691 PR c++/80691

13
gcc/testsuite/gcc.target/aarch64/sve/vcond_6.c
View File

@ -19,9 +19,12 @@
TYPE fallback, int count) \ TYPE fallback, int count) \
{ \ { \
for (int i = 0; i < count; ++i) \ for (int i = 0; i < count; ++i) \
dest[i] = (BINOP (__builtin_isunordered (a[i], b[i]), \ { \
__builtin_isunordered (c[i], d[i])) \ TYPE srcv = src[i]; \
? src[i] : fallback); \ dest[i] = (BINOP (__builtin_isunordered (a[i], b[i]), \
__builtin_isunordered (c[i], d[i])) \
? srcv : fallback); \
} \
} }
#define TEST_BINOP(T, BINOP) \ #define TEST_BINOP(T, BINOP) \
@ -40,9 +43,7 @@
TEST_ALL (LOOP) TEST_ALL (LOOP)
/* Currently we don't manage to remove ANDs from the other loops. */ /* { dg-final { scan-assembler-times {\tand\tp[0-9]+\.b, p[0-9]+/z, p[0-9]+\.b, p[0-9]+\.b} 3 } } */
/* { dg-final { scan-assembler-times {\tand\tp[0-9]+\.b, p[0-9]+/z, p[0-9]+\.b, p[0-9]+\.b} 3 { xfail *-*-* } } } */
/* { dg-final { scan-assembler {\tand\tp[0-9]+\.b, p[0-9]+/z, p[0-9]+\.b, p[0-9]+\.b} } } */
/* { dg-final { scan-assembler-times {\torr\tp[0-9]+\.b, p[0-9]+/z, p[0-9]+\.b, p[0-9]+\.b} 3 } } */ /* { dg-final { scan-assembler-times {\torr\tp[0-9]+\.b, p[0-9]+/z, p[0-9]+\.b, p[0-9]+\.b} 3 } } */
/* { dg-final { scan-assembler-times {\teor\tp[0-9]+\.b, p[0-9]+/z, p[0-9]+\.b, p[0-9]+\.b} 3 } } */ /* { dg-final { scan-assembler-times {\teor\tp[0-9]+\.b, p[0-9]+/z, p[0-9]+\.b, p[0-9]+\.b} 3 } } */
/* { dg-final { scan-assembler-times {\tnand\tp[0-9]+\.b, p[0-9]+/z, p[0-9]+\.b, p[0-9]+\.b} 3 } } */ /* { dg-final { scan-assembler-times {\tnand\tp[0-9]+\.b, p[0-9]+/z, p[0-9]+\.b, p[0-9]+\.b} 3 } } */