git
/
gcc
mirror of git://gcc.gnu.org/git/gcc.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

i386.h (ADDITIONAL_REGISTER_NAMES): Add sil, dil, bpl and spl aliases. 

* config/i386/i386.h (ADDITIONAL_REGISTER_NAMES): Add
	sil, dil, bpl and spl aliases.

From-SVN: r267456
This commit is contained in:
Uros Bizjak 2018-12-28 23:50:12 +01:00 committed by Uros Bizjak
parent 03f0fa9538
commit 50bec22834
2 changed files with 13 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
gcc/ChangeLog
View File

@ -1,3 +1,8 @@
2018-12-28 Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386.h (ADDITIONAL_REGISTER_NAMES): Add
sil, dil, bpl and spl aliases.
2018-12-28 Martin Sebor <msebor@redhat.com>
* tree-ssa-strlen.c (maybe_diag_stxncpy_trunc): Avoid
@ -71,7 +76,7 @@
parametrs.
2018-12-24 Jan Hubicka <hubicka@ucw.cz>
PR lto/88140
* tree.c (fld_simplified_type): Temporarily disable array
simplification.

21
gcc/config/i386/i386.h
View File

@ -2041,6 +2041,12 @@ do { \
#define REGISTER_NAMES HI_REGISTER_NAMES
#define QI_REGISTER_NAMES \
{"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl"}
#define QI_HIGH_REGISTER_NAMES \
{"ah", "dh", "ch", "bh"}
/* Table of additional register names to use in user input. */
#define ADDITIONAL_REGISTER_NAMES \
@ -2050,6 +2056,7 @@ do { \
{ "rax", AX_REG }, { "rdx", DX_REG }, { "rcx", CX_REG }, { "rbx", BX_REG }, \
{ "rsi", SI_REG }, { "rdi", DI_REG }, { "rbp", BP_REG }, { "rsp", SP_REG }, \
{ "al", AX_REG }, { "dl", DX_REG }, { "cl", CX_REG }, { "bl", BX_REG }, \
{ "sil", SI_REG }, { "dil", DI_REG }, { "bpl", BP_REG }, { "spl", SP_REG }, \
{ "ah", AX_REG }, { "dh", DX_REG }, { "ch", CX_REG }, { "bh", BX_REG }, \
{ "ymm0", XMM0_REG }, { "ymm1", XMM1_REG }, { "ymm2", XMM2_REG }, { "ymm3", XMM3_REG }, \
{ "ymm4", XMM4_REG }, { "ymm5", XMM5_REG }, { "ymm6", XMM6_REG }, { "ymm7", XMM7_REG }, \
@ -2069,20 +2076,6 @@ do { \
{ "zmm28", XMM28_REG }, { "zmm29", XMM29_REG }, { "zmm30", XMM30_REG }, { "zmm31", XMM31_REG } \
}
/* Note we are omitting these since currently I don't know how
to get gcc to use these, since they want the same but different
number as al, and ax.
*/
#define QI_REGISTER_NAMES \
{"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",}
/* These parallel the array above, and can be used to access bits 8:15
of regs 0 through 3. */
#define QI_HIGH_REGISTER_NAMES \
{"ah", "dh", "ch", "bh", }
/* How to renumber registers for dbx and gdb. */
#define DBX_REGISTER_NUMBER(N) \