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re PR target/68729 (../Xbae/Methods.c:1772:1: ICE: in extract_insn, at recog.c:2343) 

PR target/68729
	* config/pa/pa.c (pa_emit_move_sequence): Don't check that mode is
	consistent with modes of the input and output operands when doing
	reloads to and from floating point registers.  Do reload for all
	address forms.

From-SVN: r231482
This commit is contained in:
John David Anglin 2015-12-10 00:41:17 +00:00
parent 4cd281545e
commit 512e4ace54
2 changed files with 16 additions and 14 deletions
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8
gcc/ChangeLog
View File

@ -1,3 +1,11 @@
2015-12-09 John David Anglin <danglin@gcc.gnu.org>
PR target/68729
* config/pa/pa.c (pa_emit_move_sequence): Don't check that mode is
consistent with modes of the input and output operands when doing
reloads to and from floating point registers. Do reload for all
address forms.
2015-12-08 Jan Hubicka <hubicka@ucw.cz> 2015-12-08 Jan Hubicka <hubicka@ucw.cz>
PR ipa/61886 PR ipa/61886

22
gcc/config/pa/pa.c
View File

@ -1683,11 +1683,10 @@ pa_emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg)
REG+D addresses where D does not fit in 5 or 14 bits, including REG+D addresses where D does not fit in 5 or 14 bits, including
(subreg (mem (addr))) cases. */ (subreg (mem (addr))) cases. */
if (scratch_reg if (scratch_reg
&& fp_reg_operand (operand0, mode) && FP_REG_P (operand0)
&& (MEM_P (operand1) && (MEM_P (operand1)
|| (GET_CODE (operand1) == SUBREG || (GET_CODE (operand1) == SUBREG
&& MEM_P (XEXP (operand1, 0)))) && MEM_P (XEXP (operand1, 0)))))
&& !floating_point_store_memory_operand (operand1, mode))
{ {
if (GET_CODE (operand1) == SUBREG) if (GET_CODE (operand1) == SUBREG)
operand1 = XEXP (operand1, 0); operand1 = XEXP (operand1, 0);
@ -1699,10 +1698,8 @@ pa_emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg)
/* D might not fit in 14 bits either; for such cases load D into /* D might not fit in 14 bits either; for such cases load D into
scratch reg. */ scratch reg. */
if (reg_plus_base_memory_operand (operand1, mode) if (reg_plus_base_memory_operand (operand1, GET_MODE (operand1))
&& !(TARGET_PA_20 && !INT_14_BITS (XEXP (XEXP (operand1, 0), 1)))
&& !TARGET_ELF32
&& INT_14_BITS (XEXP (XEXP (operand1, 0), 1))))
{ {
emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1)); emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
emit_move_insn (scratch_reg, emit_move_insn (scratch_reg,
@ -1718,11 +1715,10 @@ pa_emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg)
return 1; return 1;
} }
else if (scratch_reg else if (scratch_reg
&& fp_reg_operand (operand1, mode) && FP_REG_P (operand1)
&& (MEM_P (operand0) && (MEM_P (operand0)
|| (GET_CODE (operand0) == SUBREG || (GET_CODE (operand0) == SUBREG
&& MEM_P (XEXP (operand0, 0)))) && MEM_P (XEXP (operand0, 0)))))
&& !floating_point_store_memory_operand (operand0, mode))
{ {
if (GET_CODE (operand0) == SUBREG) if (GET_CODE (operand0) == SUBREG)
operand0 = XEXP (operand0, 0); operand0 = XEXP (operand0, 0);
@ -1734,10 +1730,8 @@ pa_emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg)
/* D might not fit in 14 bits either; for such cases load D into /* D might not fit in 14 bits either; for such cases load D into
scratch reg. */ scratch reg. */
if (reg_plus_base_memory_operand (operand0, mode) if (reg_plus_base_memory_operand (operand0, GET_MODE (operand0))
&& !(TARGET_PA_20 && !INT_14_BITS (XEXP (XEXP (operand0, 0), 1)))
&& !TARGET_ELF32
&& INT_14_BITS (XEXP (XEXP (operand0, 0), 1))))
{ {
emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1)); emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1));
emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0, emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0,