git
/
gcc
mirror of git://gcc.gnu.org/git/gcc.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

rs6000: Remove paired single 

This removes paired single (used on the 750CL and friends).  It was
deprecated in GCC 8.  Removing it means we only have one vector model
to deal with (VMX+VSX, 16-byte vectors).


	* config.gcc (powerpc*-*-*): Remove paired.h.  Unsupport the
	powerpc*-*-linux*paired* target.
	* config/rs6000/750cl.h: Delete.
	* config/rs6000/paired.h: Delete.
	* config/rs6000/paired.md: Delete.
	* config/rs6000/predicates.md (easy_vector_constant): Remove paired
	float support.
	* config/rs6000/rs6000-builtin.def: Remove paired float support.
	* config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Update
	comment.  Remove paired float support.
	* config/rs6000/rs6000-modes.def: Remove V2SF and V2SI.
	* config/rs6000/rs6000-opts.h (enum rs6000_vector): Delete
	VECTOR_PAIRED.
	* config/rs6000/rs6000-protos.h (paired_expand_vector_init,
	paired_emit_vector_cond_expr, paired_expand_vector_move): Delete
	declarations.
	* config/rs6000/rs6000.c: Remove paired float support.
	(paired_expand_vector_init, paired_expand_vector_move,
	paired_emit_vector_compare, paired_emit_vector_cond_expr,
	(paired_expand_lv_builtin, paired_expand_stv_builtin,
	paired_expand_builtin, paired_expand_predicate_builtin,
	paired_init_builtins): Delete.
	* config/rs6000/rs6000.h: Remove paired float support.
	* config/rs6000/rs6000.md: Remove paired float support.
	(move_from_CR_ov_bit): Delete.
	* config/rs6000/rs6000.opt (mpaired): Delete.
	* config/rs6000/t-rs6000: Remove paired.md from MD_INCLUDES.
	* doc/invoke.texi (RS/6000 and PowerPC Options): Delete -mpaired.

From-SVN: r259833
This commit is contained in:
Segher Boessenkool 2018-05-02 12:46:00 +02:00 committed by Segher Boessenkool
parent 85b3bb6d57
commit 559289370f
17 changed files with 78 additions and 1443 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

31
gcc/ChangeLog
View File

@ -1,3 +1,34 @@
2018-05-02 Segher Boessenkool <segher@kernel.crashing.org>
* config.gcc (powerpc*-*-*): Remove paired.h. Unsupport the
powerpc*-*-linux*paired* target.
* config/rs6000/750cl.h: Delete.
* config/rs6000/paired.h: Delete.
* config/rs6000/paired.md: Delete.
* config/rs6000/predicates.md (easy_vector_constant): Remove paired
float support.
* config/rs6000/rs6000-builtin.def: Remove paired float support.
* config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Update
comment. Remove paired float support.
* config/rs6000/rs6000-modes.def: Remove V2SF and V2SI.
* config/rs6000/rs6000-opts.h (enum rs6000_vector): Delete
VECTOR_PAIRED.
* config/rs6000/rs6000-protos.h (paired_expand_vector_init,
paired_emit_vector_cond_expr, paired_expand_vector_move): Delete
declarations.
* config/rs6000/rs6000.c: Remove paired float support.
(paired_expand_vector_init, paired_expand_vector_move,
paired_emit_vector_compare, paired_emit_vector_cond_expr,
(paired_expand_lv_builtin, paired_expand_stv_builtin,
paired_expand_builtin, paired_expand_predicate_builtin,
paired_init_builtins): Delete.
* config/rs6000/rs6000.h: Remove paired float support.
* config/rs6000/rs6000.md: Remove paired float support.
(move_from_CR_ov_bit): Delete.
* config/rs6000/rs6000.opt (mpaired): Delete.
* config/rs6000/t-rs6000: Remove paired.md from MD_INCLUDES.
* doc/invoke.texi (RS/6000 and PowerPC Options): Delete -mpaired.
2018-05-02 Richard Biener <rguenther@suse.de> 2018-05-02 Richard Biener <rguenther@suse.de>
PR middle-end/85567 PR middle-end/85567

7
gcc/config.gcc
View File

@ -473,7 +473,6 @@ powerpc*-*-*)
extra_headers="${extra_headers} xmmintrin.h mm_malloc.h emmintrin.h" extra_headers="${extra_headers} xmmintrin.h mm_malloc.h emmintrin.h"
extra_headers="${extra_headers} mmintrin.h x86intrin.h" extra_headers="${extra_headers} mmintrin.h x86intrin.h"
extra_headers="${extra_headers} ppu_intrinsics.h spu2vmx.h vec_types.h si2vmx.h" extra_headers="${extra_headers} ppu_intrinsics.h spu2vmx.h vec_types.h si2vmx.h"
extra_headers="${extra_headers} paired.h"
extra_headers="${extra_headers} amo.h" extra_headers="${extra_headers} amo.h"
case x$with_cpu in case x$with_cpu in
xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[3456789]|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|xe6500) xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[3456789]|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|xe6500)
@ -2502,11 +2501,11 @@ powerpc*-*-linux*)
all) maybe_biarch=yes ;; all) maybe_biarch=yes ;;
esac esac
case ${target} in case ${target} in
powerpc64*-*-linux*spe* | powerpc64*-*-linux*paired*) powerpc64*-*-linux*spe* | powerpc*-*-linux*paired*)
echo "*** Configuration ${target} not supported" 1>&2 echo "*** Configuration ${target} not supported" 1>&2
exit 1 exit 1
;; ;;
powerpc*-*-linux*spe* | powerpc*-*-linux*paired*) powerpc*-*-linux*spe*)
maybe_biarch= maybe_biarch=
;; ;;
esac esac
@ -2552,8 +2551,6 @@ powerpc*-*-linux*)
tm_file="${tm_file} rs6000/linuxaltivec.h" ;; tm_file="${tm_file} rs6000/linuxaltivec.h" ;;
powerpc*-*-linux*spe*) powerpc*-*-linux*spe*)
tm_file="${tm_file} ${cpu_type}/linuxspe.h ${cpu_type}/e500.h" ;; tm_file="${tm_file} ${cpu_type}/linuxspe.h ${cpu_type}/e500.h" ;;
powerpc*-*-linux*paired*)
tm_file="${tm_file} rs6000/750cl.h" ;;
esac esac
case ${target} in case ${target} in
*-linux*-musl*) *-linux*-musl*)

30
gcc/config/rs6000/750cl.h
View File

@ -1,30 +0,0 @@
/* Enable 750cl paired single support.
Copyright (C) 2007-2018 Free Software Foundation, Inc.
Contributed by Revital Eres (eres@il.ibm.com)
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#undef TARGET_PAIRED_FLOAT
#define TARGET_PAIRED_FLOAT rs6000_paired_float
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC "-m750cl"

75
gcc/config/rs6000/paired.h
View File

@ -1,75 +0,0 @@
/* PowerPC 750CL user include file.
Copyright (C) 2007-2018 Free Software Foundation, Inc.
Contributed by Revital Eres (eres@il.ibm.com).
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#ifndef _PAIRED_H
#define _PAIRED_H
#define vector __attribute__((vector_size(8)))
#define paired_msub __builtin_paired_msub
#define paired_madd __builtin_paired_madd
#define paired_nmsub __builtin_paired_nmsub
#define paired_nmadd __builtin_paired_nmadd
#define paired_sum0 __builtin_paired_sum0
#define paired_sum1 __builtin_paired_sum1
#define paired_div __builtin_paired_divv2sf3
#define paired_add __builtin_paired_addv2sf3
#define paired_sub __builtin_paired_subv2sf3
#define paired_mul __builtin_paired_mulv2sf3
#define paired_muls0 __builtin_paired_muls0
#define paired_muls1 __builtin_paired_muls1
#define paired_madds0 __builtin_paired_madds0
#define paired_madds1 __builtin_paired_madds1
#define paired_merge00 __builtin_paired_merge00
#define paired_merge01 __builtin_paired_merge01
#define paired_merge10 __builtin_paired_merge10
#define paired_merge11 __builtin_paired_merge11
#define paired_abs __builtin_paired_absv2sf2
#define paired_nabs __builtin_paired_nabsv2sf2
#define paired_neg __builtin_paired_negv2sf2
#define paired_sqrt __builtin_paired_sqrtv2sf2
#define paired_res __builtin_paired_resv2sf2
#define paired_stx __builtin_paired_stx
#define paired_lx __builtin_paired_lx
#define paired_cmpu0 __builtin_paired_cmpu0
#define paired_cmpu1 __builtin_paired_cmpu1
#define paired_sel __builtin_paired_selv2sf4
/* Condition register codes for Paired predicates. */
#define LT 0
#define GT 1
#define EQ 2
#define UN 3
#define paired_cmpu0_un(a,b) __builtin_paired_cmpu0 (UN, (a), (b))
#define paired_cmpu0_eq(a,b) __builtin_paired_cmpu0 (EQ, (a), (b))
#define paired_cmpu0_lt(a,b) __builtin_paired_cmpu0 (LT, (a), (b))
#define paired_cmpu0_gt(a,b) __builtin_paired_cmpu0 (GT, (a), (b))
#define paired_cmpu1_un(a,b) __builtin_paired_cmpu1 (UN, (a), (b))
#define paired_cmpu1_eq(a,b) __builtin_paired_cmpu1 (EQ, (a), (b))
#define paired_cmpu1_lt(a,b) __builtin_paired_cmpu1 (LT, (a), (b))
#define paired_cmpu1_gt(a,b) __builtin_paired_cmpu1 (GT, (a), (b))
#endif /* _PAIRED_H */

492
gcc/config/rs6000/paired.md
View File

@ -1,492 +0,0 @@
;; PowerPC paired single and double hummer description
;; Copyright (C) 2007-2018 Free Software Foundation, Inc.
;; Contributed by David Edelsohn <edelsohn@gnu.org> and Revital Eres
;; <eres@il.ibm.com>
;; This file is part of GCC.
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.
;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
;; License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with this program; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
(define_c_enum "unspec"
[UNSPEC_INTERHI_V2SF
UNSPEC_INTERLO_V2SF
UNSPEC_EXTEVEN_V2SF
UNSPEC_EXTODD_V2SF
])
(define_insn "negv2sf2"
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
(neg:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "f")))]
"TARGET_PAIRED_FLOAT"
"ps_neg %0,%1"
[(set_attr "type" "fp")])
(define_insn "sqrtv2sf2"
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
(sqrt:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "f")))]
"TARGET_PAIRED_FLOAT"
"ps_rsqrte %0,%1"
[(set_attr "type" "fp")])
(define_insn "absv2sf2"
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
(abs:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "f")))]
"TARGET_PAIRED_FLOAT"
"ps_abs %0,%1"
[(set_attr "type" "fp")])
(define_insn "nabsv2sf2"
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
(neg:V2SF (abs:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "f"))))]
"TARGET_PAIRED_FLOAT"
"ps_nabs %0,%1"
[(set_attr "type" "fp")])
(define_insn "addv2sf3"
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
(plus:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "%f")
(match_operand:V2SF 2 "gpc_reg_operand" "f")))]
"TARGET_PAIRED_FLOAT"
"ps_add %0,%1,%2"
[(set_attr "type" "fp")])
(define_insn "subv2sf3"
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
(minus:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "f")
(match_operand:V2SF 2 "gpc_reg_operand" "f")))]
"TARGET_PAIRED_FLOAT"
"ps_sub %0,%1,%2"
[(set_attr "type" "fp")])
(define_insn "mulv2sf3"
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
(mult:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "%f")
(match_operand:V2SF 2 "gpc_reg_operand" "f")))]
"TARGET_PAIRED_FLOAT"
"ps_mul %0,%1,%2"
[(set_attr "type" "fp")])
(define_insn "resv2sf2"
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
(unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
"TARGET_PAIRED_FLOAT && flag_finite_math_only"
"ps_res %0,%1"
[(set_attr "type" "fp")])
(define_insn "divv2sf3"
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
(div:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "f")
(match_operand:V2SF 2 "gpc_reg_operand" "f")))]
"TARGET_PAIRED_FLOAT"
"ps_div %0,%1,%2"
[(set_attr "type" "sdiv")])
(define_insn "paired_madds0"
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
(vec_concat:V2SF
(fma:SF
(vec_select:SF (match_operand:V2SF 1 "gpc_reg_operand" "f")
(parallel [(const_int 0)]))
(vec_select:SF (match_operand:V2SF 2 "gpc_reg_operand" "f")
(parallel [(const_int 0)]))
(vec_select:SF (match_operand:V2SF 3 "gpc_reg_operand" "f")
(parallel [(const_int 0)])))
(fma:SF
(vec_select:SF (match_dup 1)
(parallel [(const_int 1)]))
(vec_select:SF (match_dup 2)
(parallel [(const_int 0)]))
(vec_select:SF (match_dup 3)
(parallel [(const_int 1)])))))]
"TARGET_PAIRED_FLOAT"
"ps_madds0 %0,%1,%2,%3"
[(set_attr "type" "fp")])
(define_insn "paired_madds1"
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
(vec_concat:V2SF
(fma:SF
(vec_select:SF (match_operand:V2SF 1 "gpc_reg_operand" "f")
(parallel [(const_int 0)]))
(vec_select:SF (match_operand:V2SF 2 "gpc_reg_operand" "f")
(parallel [(const_int 1)]))
(vec_select:SF (match_operand:V2SF 3 "gpc_reg_operand" "f")
(parallel [(const_int 0)])))
(fma:SF
(vec_select:SF (match_dup 1)
(parallel [(const_int 1)]))
(vec_select:SF (match_dup 2)
(parallel [(const_int 1)]))
(vec_select:SF (match_dup 3)
(parallel [(const_int 1)])))))]
"TARGET_PAIRED_FLOAT"
"ps_madds1 %0,%1,%2,%3"
[(set_attr "type" "fp")])
(define_insn "*paired_madd"
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
(fma:V2SF
(match_operand:V2SF 1 "gpc_reg_operand" "f")
(match_operand:V2SF 2 "gpc_reg_operand" "f")
(match_operand:V2SF 3 "gpc_reg_operand" "f")))]
"TARGET_PAIRED_FLOAT"
"ps_madd %0,%1,%2,%3"
[(set_attr "type" "fp")])
(define_insn "*paired_msub"
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
(fma:V2SF
(match_operand:V2SF 1 "gpc_reg_operand" "f")
(match_operand:V2SF 2 "gpc_reg_operand" "f")
(neg:V2SF (match_operand:V2SF 3 "gpc_reg_operand" "f"))))]
"TARGET_PAIRED_FLOAT"
"ps_msub %0,%1,%2,%3"
[(set_attr "type" "fp")])
(define_insn "*paired_nmadd"
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
(neg:V2SF
(fma:V2SF
(match_operand:V2SF 1 "gpc_reg_operand" "f")
(match_operand:V2SF 2 "gpc_reg_operand" "f")
(match_operand:V2SF 3 "gpc_reg_operand" "f"))))]
"TARGET_PAIRED_FLOAT"
"ps_nmadd %0,%1,%2,%3"
[(set_attr "type" "fp")])
(define_insn "*paired_nmsub"
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
(neg:V2SF
(fma:V2SF
(match_operand:V2SF 1 "gpc_reg_operand" "f")
(match_operand:V2SF 2 "gpc_reg_operand" "f")
(neg:V2SF (match_operand:V2SF 3 "gpc_reg_operand" "f")))))]
"TARGET_PAIRED_FLOAT"
"ps_nmsub %0,%1,%2,%3"
[(set_attr "type" "dmul")])
(define_insn "selv2sf4"
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
(vec_concat:V2SF
(if_then_else:SF (ge (vec_select:SF (match_operand:V2SF 1 "gpc_reg_operand" "f")
(parallel [(const_int 0)]))
(match_operand:SF 4 "zero_fp_constant" "F"))
(vec_select:SF (match_operand:V2SF 2 "gpc_reg_operand" "f")
(parallel [(const_int 0)]))
(vec_select:SF (match_operand:V2SF 3 "gpc_reg_operand" "f")
(parallel [(const_int 0)])))
(if_then_else:SF (ge (vec_select:SF (match_dup 1)
(parallel [(const_int 1)]))
(match_dup 4))
(vec_select:SF (match_dup 2)
(parallel [(const_int 1)]))
(vec_select:SF (match_dup 3)
(parallel [(const_int 1)])))))]
"TARGET_PAIRED_FLOAT"
"ps_sel %0,%1,%2,%3"
[(set_attr "type" "fp")])
(define_insn "*movv2sf_paired"
[(set (match_operand:V2SF 0 "nonimmediate_operand" "=Z,f,f,Y,r,r,f")
(match_operand:V2SF 1 "input_operand" "f,Z,f,r,Y,r,W"))]
"TARGET_PAIRED_FLOAT
&& (register_operand (operands[0], V2SFmode)
|| register_operand (operands[1], V2SFmode))"
{
switch (which_alternative)
{
case 0: return "psq_stx %1,%y0,0,0";
case 1: return "psq_lx %0,%y1,0,0";
case 2: return "ps_mr %0,%1";
case 3: return "#";
case 4: return "#";
case 5: return "#";
case 6: return "#";
default: gcc_unreachable ();
}
}
[(set_attr "type" "fpstore,fpload,fp,*,*,*,*")])
(define_insn "paired_stx"
[(set (match_operand:V2SF 0 "memory_operand" "=Z")
(match_operand:V2SF 1 "gpc_reg_operand" "f"))]
"TARGET_PAIRED_FLOAT"
"psq_stx %1,%y0,0,0"
[(set_attr "type" "fpstore")])
(define_insn "paired_lx"
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
(match_operand:V2SF 1 "memory_operand" "Z"))]
"TARGET_PAIRED_FLOAT"
"psq_lx %0,%y1,0,0"
[(set_attr "type" "fpload")])
(define_split
[(set (match_operand:V2SF 0 "nonimmediate_operand" "")
(match_operand:V2SF 1 "input_operand" ""))]
"TARGET_PAIRED_FLOAT && reload_completed
&& gpr_or_gpr_p (operands[0], operands[1])"
[(pc)]
{
rs6000_split_multireg_move (operands[0], operands[1]); DONE;
})
(define_insn "paired_cmpu0"
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
(compare:CCFP (vec_select:SF
(match_operand:V2SF 1 "gpc_reg_operand" "f")
(parallel [(const_int 0)]))
(vec_select:SF
(match_operand:V2SF 2 "gpc_reg_operand" "f")
(parallel [(const_int 0)]))))]
"TARGET_PAIRED_FLOAT"
"ps_cmpu0 %0,%1,%2"
[(set_attr "type" "fpcompare")])
(define_insn "paired_cmpu1"
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
(compare:CCFP (vec_select:SF
(match_operand:V2SF 1 "gpc_reg_operand" "f")
(parallel [(const_int 1)]))
(vec_select:SF
(match_operand:V2SF 2 "gpc_reg_operand" "f")
(parallel [(const_int 1)]))))]
"TARGET_PAIRED_FLOAT"
"ps_cmpu1 %0,%1,%2"
[(set_attr "type" "fpcompare")])
(define_insn "paired_merge00"
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
(vec_select:V2SF
(vec_concat:V4SF
(match_operand:V2SF 1 "gpc_reg_operand" "f")
(match_operand:V2SF 2 "gpc_reg_operand" "f"))
(parallel [(const_int 0) (const_int 2)])))]
"TARGET_PAIRED_FLOAT"
"ps_merge00 %0, %1, %2"
[(set_attr "type" "fp")])
(define_insn "paired_merge01"
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
(vec_select:V2SF
(vec_concat:V4SF
(match_operand:V2SF 1 "gpc_reg_operand" "f")
(match_operand:V2SF 2 "gpc_reg_operand" "f"))
(parallel [(const_int 0) (const_int 3)])))]
"TARGET_PAIRED_FLOAT"
"ps_merge01 %0, %1, %2"
[(set_attr "type" "fp")])
(define_insn "paired_merge10"
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
(vec_select:V2SF
(vec_concat:V4SF
(match_operand:V2SF 1 "gpc_reg_operand" "f")
(match_operand:V2SF 2 "gpc_reg_operand" "f"))
(parallel [(const_int 1) (const_int 2)])))]
"TARGET_PAIRED_FLOAT"
"ps_merge10 %0, %1, %2"
[(set_attr "type" "fp")])
(define_insn "paired_merge11"
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
(vec_select:V2SF
(vec_concat:V4SF
(match_operand:V2SF 1 "gpc_reg_operand" "f")
(match_operand:V2SF 2 "gpc_reg_operand" "f"))
(parallel [(const_int 1) (const_int 3)])))]
"TARGET_PAIRED_FLOAT"
"ps_merge11 %0, %1, %2"
[(set_attr "type" "fp")])
(define_insn "paired_sum0"
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
(vec_concat:V2SF (plus:SF (vec_select:SF
(match_operand:V2SF 1 "gpc_reg_operand" "f")
(parallel [(const_int 0)]))
(vec_select:SF
(match_operand:V2SF 2 "gpc_reg_operand" "f")
(parallel [(const_int 1)])))
(vec_select:SF
(match_operand:V2SF 3 "gpc_reg_operand" "f")
(parallel [(const_int 1)]))))]
"TARGET_PAIRED_FLOAT"
"ps_sum0 %0,%1,%2,%3"
[(set_attr "type" "fp")])
(define_insn "paired_sum1"
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
(vec_concat:V2SF (vec_select:SF
(match_operand:V2SF 2 "gpc_reg_operand" "f")
(parallel [(const_int 1)]))
(plus:SF (vec_select:SF
(match_operand:V2SF 1 "gpc_reg_operand" "f")
(parallel [(const_int 0)]))
(vec_select:SF
(match_operand:V2SF 3 "gpc_reg_operand" "f")
(parallel [(const_int 1)])))))]
"TARGET_PAIRED_FLOAT"
"ps_sum1 %0,%1,%2,%3"
[(set_attr "type" "fp")])
(define_insn "paired_muls0"
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
(mult:V2SF (match_operand:V2SF 2 "gpc_reg_operand" "f")
(vec_duplicate:V2SF
(vec_select:SF (match_operand:V2SF 1 "gpc_reg_operand" "f")
(parallel [(const_int 0)])))))]
"TARGET_PAIRED_FLOAT"
"ps_muls0 %0, %1, %2"
[(set_attr "type" "fp")])
(define_insn "paired_muls1"
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
(mult:V2SF (match_operand:V2SF 2 "gpc_reg_operand" "f")
(vec_duplicate:V2SF
(vec_select:SF (match_operand:V2SF 1 "gpc_reg_operand" "f")
(parallel [(const_int 1)])))))]
"TARGET_PAIRED_FLOAT"
"ps_muls1 %0, %1, %2"
[(set_attr "type" "fp")])
(define_expand "vec_initv2sfsf"
[(match_operand:V2SF 0 "gpc_reg_operand" "=f")
(match_operand 1 "" "")]
"TARGET_PAIRED_FLOAT"
{
paired_expand_vector_init (operands[0], operands[1]);
DONE;
})
(define_insn "*vconcatsf"
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
(vec_concat:V2SF
(match_operand:SF 1 "gpc_reg_operand" "f")
(match_operand:SF 2 "gpc_reg_operand" "f")))]
"TARGET_PAIRED_FLOAT"
"ps_merge00 %0, %1, %2"
[(set_attr "type" "fp")])
(define_expand "sminv2sf3"
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
(smin:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "f")
(match_operand:V2SF 2 "gpc_reg_operand" "f")))]
"TARGET_PAIRED_FLOAT"
{
rtx tmp = gen_reg_rtx (V2SFmode);
emit_insn (gen_subv2sf3 (tmp, operands[1], operands[2]));
emit_insn (gen_selv2sf4 (operands[0], tmp, operands[2], operands[1], CONST0_RTX (SFmode)));
DONE;
})
(define_expand "smaxv2sf3"
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
(smax:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "f")
(match_operand:V2SF 2 "gpc_reg_operand" "f")))]
"TARGET_PAIRED_FLOAT"
{
rtx tmp = gen_reg_rtx (V2SFmode);
emit_insn (gen_subv2sf3 (tmp, operands[1], operands[2]));
emit_insn (gen_selv2sf4 (operands[0], tmp, operands[1], operands[2], CONST0_RTX (SFmode)));
DONE;
})
(define_expand "reduc_smax_scal_v2sf"
[(match_operand:SF 0 "gpc_reg_operand" "=f")
(match_operand:V2SF 1 "gpc_reg_operand" "f")]
"TARGET_PAIRED_FLOAT"
{
rtx tmp_swap = gen_reg_rtx (V2SFmode);
rtx tmp = gen_reg_rtx (V2SFmode);
rtx vec_res = gen_reg_rtx (V2SFmode);
rtx di_res = gen_reg_rtx (DImode);
emit_insn (gen_paired_merge10 (tmp_swap, operands[1], operands[1]));
emit_insn (gen_subv2sf3 (tmp, operands[1], tmp_swap));
emit_insn (gen_selv2sf4 (vec_res, tmp, operands[1], tmp_swap,
CONST0_RTX (SFmode)));
emit_move_insn (di_res, simplify_gen_subreg (DImode, vec_res, V2SFmode, 0));
emit_move_insn (operands[0], simplify_gen_subreg (SFmode, di_res, DImode,
BYTES_BIG_ENDIAN ? 4 : 0));
DONE;
})
(define_expand "reduc_smin_scal_v2sf"
[(match_operand:SF 0 "gpc_reg_operand" "=f")
(match_operand:V2SF 1 "gpc_reg_operand" "f")]
"TARGET_PAIRED_FLOAT"
{
rtx tmp_swap = gen_reg_rtx (V2SFmode);
rtx tmp = gen_reg_rtx (V2SFmode);
rtx vec_res = gen_reg_rtx (V2SFmode);
rtx di_res = gen_reg_rtx (DImode);
emit_insn (gen_paired_merge10 (tmp_swap, operands[1], operands[1]));
emit_insn (gen_subv2sf3 (tmp, operands[1], tmp_swap));
emit_insn (gen_selv2sf4 (vec_res, tmp, tmp_swap, operands[1],
CONST0_RTX (SFmode)));
emit_move_insn (di_res, simplify_gen_subreg (DImode, vec_res, V2SFmode, 0));
emit_move_insn (operands[0], simplify_gen_subreg (SFmode, di_res, DImode,
BYTES_BIG_ENDIAN ? 4 : 0));
DONE;
})
(define_expand "reduc_plus_scal_v2sf"
[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(match_operand:V2SF 1 "gpc_reg_operand" "f"))]
"TARGET_PAIRED_FLOAT"
{
rtx vec_res = gen_reg_rtx (V2SFmode);
rtx di_res = gen_reg_rtx (DImode);
emit_insn (gen_paired_sum1 (vec_res, operands[1], operands[1], operands[1]));
emit_move_insn (di_res, simplify_gen_subreg (DImode, vec_res, V2SFmode, 0));
emit_move_insn (operands[0], simplify_gen_subreg (SFmode, di_res, DImode,
BYTES_BIG_ENDIAN ? 4 : 0));
DONE;
})
(define_expand "movmisalignv2sf"
[(set (match_operand:V2SF 0 "nonimmediate_operand" "")
(match_operand:V2SF 1 "any_operand" ""))]
"TARGET_PAIRED_FLOAT"
{
paired_expand_vector_move (operands);
DONE;
})
(define_expand "vcondv2sfv2sf"
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
(if_then_else:V2SF
(match_operator 3 "gpc_reg_operand"
[(match_operand:V2SF 4 "gpc_reg_operand" "f")
(match_operand:V2SF 5 "gpc_reg_operand" "f")])
(match_operand:V2SF 1 "gpc_reg_operand" "f")
(match_operand:V2SF 2 "gpc_reg_operand" "f")))]
"TARGET_PAIRED_FLOAT && flag_unsafe_math_optimizations"
{
if (paired_emit_vector_cond_expr (operands[0], operands[1], operands[2],
operands[3], operands[4], operands[5]))
DONE;
else
FAIL;
})

5
gcc/config/rs6000/predicates.md
View File

@ -690,11 +690,6 @@
(define_predicate "easy_vector_constant" (define_predicate "easy_vector_constant"
(match_code "const_vector") (match_code "const_vector")
{ {
/* As the paired vectors are actually FPRs it seems that there is
no easy way to load a CONST_VECTOR without using memory. */
if (TARGET_PAIRED_FLOAT)
return false;
/* Because IEEE 128-bit floating point is considered a vector type /* Because IEEE 128-bit floating point is considered a vector type
in order to pass it in VSX registers, it might use this function in order to pass it in VSX registers, it might use this function
instead of easy_fp_constant. */ instead of easy_fp_constant. */

84
gcc/config/rs6000/rs6000-builtin.def
View File

@ -32,7 +32,6 @@
RS6000_BUILTIN_D -- DST builtins RS6000_BUILTIN_D -- DST builtins
RS6000_BUILTIN_H -- HTM builtins RS6000_BUILTIN_H -- HTM builtins
RS6000_BUILTIN_P -- Altivec, VSX, ISA 2.07 vector predicate builtins RS6000_BUILTIN_P -- Altivec, VSX, ISA 2.07 vector predicate builtins
RS6000_BUILTIN_Q -- Paired floating point VSX predicate builtins
RS6000_BUILTIN_X -- special builtins RS6000_BUILTIN_X -- special builtins
Each of the above macros takes 4 arguments: Each of the above macros takes 4 arguments:
@ -74,10 +73,6 @@
#error "RS6000_BUILTIN_P is not defined." #error "RS6000_BUILTIN_P is not defined."
#endif #endif
#ifndef RS6000_BUILTIN_Q
#error "RS6000_BUILTIN_Q is not defined."
#endif
#ifndef RS6000_BUILTIN_X #ifndef RS6000_BUILTIN_X
#error "RS6000_BUILTIN_X is not defined." #error "RS6000_BUILTIN_X is not defined."
#endif #endif
@ -549,47 +544,6 @@
| RS6000_BTC_VOID), \ | RS6000_BTC_VOID), \
CODE_FOR_ ## ICODE) /* ICODE */ CODE_FOR_ ## ICODE) /* ICODE */
/* Paired floating point convenience macros. */
#define BU_PAIRED_1(ENUM, NAME, ATTR, ICODE) \
RS6000_BUILTIN_1 (PAIRED_BUILTIN_ ## ENUM, /* ENUM */ \
"__builtin_paired_" NAME, /* NAME */ \
RS6000_BTM_PAIRED, /* MASK */ \
(RS6000_BTC_ ## ATTR /* ATTR */ \
| RS6000_BTC_UNARY), \
CODE_FOR_ ## ICODE) /* ICODE */
#define BU_PAIRED_2(ENUM, NAME, ATTR, ICODE) \
RS6000_BUILTIN_2 (PAIRED_BUILTIN_ ## ENUM, /* ENUM */ \
"__builtin_paired_" NAME, /* NAME */ \
RS6000_BTM_PAIRED, /* MASK */ \
(RS6000_BTC_ ## ATTR /* ATTR */ \
| RS6000_BTC_BINARY), \
CODE_FOR_ ## ICODE) /* ICODE */
#define BU_PAIRED_3(ENUM, NAME, ATTR, ICODE) \
RS6000_BUILTIN_3 (PAIRED_BUILTIN_ ## ENUM, /* ENUM */ \
"__builtin_paired_" NAME, /* NAME */ \
RS6000_BTM_PAIRED, /* MASK */ \
(RS6000_BTC_ ## ATTR /* ATTR */ \
| RS6000_BTC_TERNARY), \
CODE_FOR_ ## ICODE) /* ICODE */
#define BU_PAIRED_P(ENUM, NAME, ATTR, ICODE) \
RS6000_BUILTIN_Q (PAIRED_BUILTIN_ ## ENUM, /* ENUM */ \
"__builtin_paired_" NAME, /* NAME */ \
RS6000_BTM_PAIRED, /* MASK */ \
(RS6000_BTC_ ## ATTR /* ATTR */ \
| RS6000_BTC_PREDICATE), \
CODE_FOR_ ## ICODE) /* ICODE */
#define BU_PAIRED_X(ENUM, NAME, ATTR) \
RS6000_BUILTIN_X (PAIRED_BUILTIN_ ## ENUM, /* ENUM */ \
"__builtin_paired_" NAME, /* NAME */ \
RS6000_BTM_PAIRED, /* MASK */ \
(RS6000_BTC_ ## ATTR /* ATTR */ \
| RS6000_BTC_SPECIAL), \
CODE_FOR_nothing) /* ICODE */
#define BU_SPECIAL_X(ENUM, NAME, MASK, ATTR) \ #define BU_SPECIAL_X(ENUM, NAME, MASK, ATTR) \
RS6000_BUILTIN_X (ENUM, /* ENUM */ \ RS6000_BUILTIN_X (ENUM, /* ENUM */ \
NAME, /* NAME */ \ NAME, /* NAME */ \
@ -2480,44 +2434,6 @@ BU_HTM_V1 (SET_TEXASR, "set_texasr", SPR, nothing)
BU_HTM_0 (GET_TEXASRU, "get_texasru", SPR, nothing) BU_HTM_0 (GET_TEXASRU, "get_texasru", SPR, nothing)
BU_HTM_V1 (SET_TEXASRU, "set_texasru", SPR, nothing) BU_HTM_V1 (SET_TEXASRU, "set_texasru", SPR, nothing)
/* 3 argument paired floating point builtins. */
BU_PAIRED_3 (MSUB, "msub", FP, fmsv2sf4)
BU_PAIRED_3 (MADD, "madd", FP, fmav2sf4)
BU_PAIRED_3 (MADDS0, "madds0", FP, paired_madds0)
BU_PAIRED_3 (MADDS1, "madds1", FP, paired_madds1)
BU_PAIRED_3 (NMSUB, "nmsub", FP, nfmsv2sf4)
BU_PAIRED_3 (NMADD, "nmadd", FP, nfmav2sf4)
BU_PAIRED_3 (SUM0, "sum0", FP, paired_sum0)
BU_PAIRED_3 (SUM1, "sum1", FP, paired_sum1)
BU_PAIRED_3 (SELV2SF4, "selv2sf4", CONST, selv2sf4)
/* 2 argument paired floating point builtins. */
BU_PAIRED_2 (DIVV2SF3, "divv2sf3", FP, divv2sf3)
BU_PAIRED_2 (ADDV2SF3, "addv2sf3", FP, addv2sf3)
BU_PAIRED_2 (SUBV2SF3, "subv2sf3", FP, subv2sf3)
BU_PAIRED_2 (MULV2SF3, "mulv2sf3", FP, mulv2sf3)
BU_PAIRED_2 (MULS0, "muls0", FP, paired_muls0)
BU_PAIRED_2 (MULS1, "muls1", FP, paired_muls1)
BU_PAIRED_2 (MERGE00, "merge00", CONST, paired_merge00)
BU_PAIRED_2 (MERGE01, "merge01", CONST, paired_merge01)
BU_PAIRED_2 (MERGE10, "merge10", CONST, paired_merge10)
BU_PAIRED_2 (MERGE11, "merge11", CONST, paired_merge11)
/* 1 argument paired floating point builtin functions. */
BU_PAIRED_1 (ABSV2SF2, "absv2sf2", CONST, absv2sf2)
BU_PAIRED_1 (NABSV2SF2, "nabsv2sf2", CONST, nabsv2sf2)
BU_PAIRED_1 (NEGV2SF2, "negv2sf2", CONST, negv2sf2)
BU_PAIRED_1 (SQRTV2SF2, "sqrtv2sf2", FP, sqrtv2sf2)
BU_PAIRED_1 (RESV2SF, "resv2sf2", FP, resv2sf2)
/* PAIRED builtins that are handled as special cases. */
BU_PAIRED_X (STX, "stx", MISC)
BU_PAIRED_X (LX, "lx", MISC)
/* Paired predicates. */
BU_PAIRED_P (CMPU0, "cmpu0", CONST, paired_cmpu0)
BU_PAIRED_P (CMPU1, "cmpu1", CONST, paired_cmpu1)
/* Power7 builtins, that aren't VSX instructions. */ /* Power7 builtins, that aren't VSX instructions. */
BU_SPECIAL_X (POWER7_BUILTIN_BPERMD, "__builtin_bpermd", RS6000_BTM_POPCNTD, BU_SPECIAL_X (POWER7_BUILTIN_BPERMD, "__builtin_bpermd", RS6000_BTM_POPCNTD,

13
gcc/config/rs6000/rs6000-c.c
View File

@ -494,17 +494,14 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags,
or TARGET_DOUBLE_FLOAT are turned off. Hereafter, the or TARGET_DOUBLE_FLOAT are turned off. Hereafter, the
OPTION_MASK_VSX flag is considered to have been turned off OPTION_MASK_VSX flag is considered to have been turned off
explicitly. explicitly.
3. If TARGET_PAIRED_FLOAT was enabled. Hereafter, the 3. If TARGET_AVOID_XFORM is turned on explicitly at the outermost
OPTION_MASK_VSX flag is considered to have been turned off
explicitly.
4. If TARGET_AVOID_XFORM is turned on explicitly at the outermost
compilation context, or if it is turned on by any means in an compilation context, or if it is turned on by any means in an
inner compilation context. Hereafter, the OPTION_MASK_VSX inner compilation context. Hereafter, the OPTION_MASK_VSX
flag is considered to have been turned off explicitly. flag is considered to have been turned off explicitly.
5. If TARGET_ALTIVEC was explicitly disabled. Hereafter, the 4. If TARGET_ALTIVEC was explicitly disabled. Hereafter, the
OPTION_MASK_VSX flag is considered to have been turned off OPTION_MASK_VSX flag is considered to have been turned off
explicitly. explicitly.
6. If an inner context (as introduced by 5. If an inner context (as introduced by
__attribute__((__target__())) or #pragma GCC target() __attribute__((__target__())) or #pragma GCC target()
requests a target that normally enables the requests a target that normally enables the
OPTION_MASK_VSX flag but the outer-most "main target" OPTION_MASK_VSX flag but the outer-most "main target"
@ -590,10 +587,6 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags,
rs6000_define_or_undefine_macro (define_p, "__FLOAT128_HARDWARE__"); rs6000_define_or_undefine_macro (define_p, "__FLOAT128_HARDWARE__");
/* options from the builtin masks. */ /* options from the builtin masks. */
/* Note that RS6000_BTM_PAIRED is enabled only if
TARGET_PAIRED_FLOAT is enabled (e.g. -mpaired). */
if ((bu_mask & RS6000_BTM_PAIRED) != 0)
rs6000_define_or_undefine_macro (define_p, "__PAIRED__");
/* Note that RS6000_BTM_CELL is enabled only if (rs6000_cpu == /* Note that RS6000_BTM_CELL is enabled only if (rs6000_cpu ==
PROCESSOR_CELL) (e.g. -mcpu=cell). */ PROCESSOR_CELL) (e.g. -mcpu=cell). */
if ((bu_mask & RS6000_BTM_CELL) != 0) if ((bu_mask & RS6000_BTM_CELL) != 0)

4
gcc/config/rs6000/rs6000-modes.def
View File

@ -51,10 +51,6 @@ VECTOR_MODES (FLOAT, 16); /* V8HF V4SF V2DF */
VECTOR_MODES (INT, 32); /* V32QI V16HI V8SI V4DI */ VECTOR_MODES (INT, 32); /* V32QI V16HI V8SI V4DI */
VECTOR_MODES (FLOAT, 32); /* V16HF V8SF V4DF */ VECTOR_MODES (FLOAT, 32); /* V16HF V8SF V4DF */
/* Paired single. */
VECTOR_MODE (FLOAT, SF, 2); /* The only valid paired-single mode. */
VECTOR_MODE (INT, SI, 2); /* For paired-single permutes. */
/* Replacement for TImode that only is allowed in GPRs. We also use PTImode /* Replacement for TImode that only is allowed in GPRs. We also use PTImode
for quad memory atomic operations to force getting an even/odd register for quad memory atomic operations to force getting an even/odd register
combination. */ combination. */

1
gcc/config/rs6000/rs6000-opts.h
View File

@ -149,7 +149,6 @@ enum rs6000_vector {
VECTOR_ALTIVEC, /* Use altivec for vector processing */ VECTOR_ALTIVEC, /* Use altivec for vector processing */
VECTOR_VSX, /* Use VSX for vector processing */ VECTOR_VSX, /* Use VSX for vector processing */
VECTOR_P8_VECTOR, /* Use ISA 2.07 VSX for vector processing */ VECTOR_P8_VECTOR, /* Use ISA 2.07 VSX for vector processing */
VECTOR_PAIRED, /* Use paired floating point for vectors */
VECTOR_OTHER /* Some other vector unit */ VECTOR_OTHER /* Some other vector unit */
}; };

4
gcc/config/rs6000/rs6000-protos.h
View File

@ -57,7 +57,6 @@ extern bool rs6000_move_128bit_ok_p (rtx []);
extern bool rs6000_split_128bit_ok_p (rtx []); extern bool rs6000_split_128bit_ok_p (rtx []);
extern void rs6000_expand_float128_convert (rtx, rtx, bool); extern void rs6000_expand_float128_convert (rtx, rtx, bool);
extern void rs6000_expand_vector_init (rtx, rtx); extern void rs6000_expand_vector_init (rtx, rtx);
extern void paired_expand_vector_init (rtx, rtx);
extern void rs6000_expand_vector_set (rtx, rtx, int); extern void rs6000_expand_vector_set (rtx, rtx, int);
extern void rs6000_expand_vector_extract (rtx, rtx, rtx); extern void rs6000_expand_vector_extract (rtx, rtx, rtx);
extern void rs6000_split_vec_extract_var (rtx, rtx, rtx, rtx, rtx); extern void rs6000_split_vec_extract_var (rtx, rtx, rtx, rtx, rtx);
@ -110,9 +109,6 @@ extern enum reg_class (*rs6000_secondary_reload_class_ptr) (enum reg_class,
rtx); rtx);
extern void rs6000_secondary_reload_inner (rtx, rtx, rtx, bool); extern void rs6000_secondary_reload_inner (rtx, rtx, rtx, bool);
extern void rs6000_secondary_reload_gpr (rtx, rtx, rtx, bool); extern void rs6000_secondary_reload_gpr (rtx, rtx, rtx, bool);
extern int paired_emit_vector_cond_expr (rtx, rtx, rtx,
rtx, rtx, rtx);
extern void paired_expand_vector_move (rtx operands[]);
extern int ccr_bit (rtx, int); extern int ccr_bit (rtx, int);

698
gcc/config/rs6000/rs6000.c
View File

File diff suppressed because it is too large Load Diff

50
gcc/config/rs6000/rs6000.h
View File

@ -67,10 +67,6 @@
#define PPC405_ERRATUM77 0 #define PPC405_ERRATUM77 0
#endif #endif
#ifndef TARGET_PAIRED_FLOAT
#define TARGET_PAIRED_FLOAT 0
#endif
#ifdef HAVE_AS_POPCNTB #ifdef HAVE_AS_POPCNTB
#define ASM_CPU_POWER5_SPEC "-mpower5" #define ASM_CPU_POWER5_SPEC "-mpower5"
#else #else
@ -695,19 +691,16 @@ extern int rs6000_vector_align[];
/* For power systems, we want to enable Altivec and VSX builtins even if the /* For power systems, we want to enable Altivec and VSX builtins even if the
user did not use -maltivec or -mvsx to allow the builtins to be used inside user did not use -maltivec or -mvsx to allow the builtins to be used inside
of #pragma GCC target or the target attribute to change the code level for a of #pragma GCC target or the target attribute to change the code level for a
given system. The Paired builtins are only enabled if you configure the given system. */
compiler for those builtins, and those machines don't support altivec or
VSX. */
#define TARGET_EXTRA_BUILTINS (!TARGET_PAIRED_FLOAT \ #define TARGET_EXTRA_BUILTINS (TARGET_POWERPC64 \
&& ((TARGET_POWERPC64 \ || TARGET_PPC_GPOPT /* 970/power4 */ \
|| TARGET_PPC_GPOPT /* 970/power4 */ \ || TARGET_POPCNTB /* ISA 2.02 */ \
|| TARGET_POPCNTB /* ISA 2.02 */ \ || TARGET_CMPB /* ISA 2.05 */ \
|| TARGET_CMPB /* ISA 2.05 */ \ || TARGET_POPCNTD /* ISA 2.06 */ \
|| TARGET_POPCNTD /* ISA 2.06 */ \ || TARGET_ALTIVEC \
|| TARGET_ALTIVEC \ || TARGET_VSX \
|| TARGET_VSX \ || TARGET_HARD_FLOAT)
|| TARGET_HARD_FLOAT)))
/* E500 cores only support plain "sync", not lwsync. */ /* E500 cores only support plain "sync", not lwsync. */
#define TARGET_NO_LWSYNC (rs6000_cpu == PROCESSOR_PPC8540 \ #define TARGET_NO_LWSYNC (rs6000_cpu == PROCESSOR_PPC8540 \
@ -863,7 +856,6 @@ extern unsigned char rs6000_recip_bits[];
#define UNITS_PER_FP_WORD 8 #define UNITS_PER_FP_WORD 8
#define UNITS_PER_ALTIVEC_WORD 16 #define UNITS_PER_ALTIVEC_WORD 16
#define UNITS_PER_VSX_WORD 16 #define UNITS_PER_VSX_WORD 16
#define UNITS_PER_PAIRED_WORD 8
/* Type used for ptrdiff_t, as a string used in a declaration. */ /* Type used for ptrdiff_t, as a string used in a declaration. */
#define PTRDIFF_TYPE "int" #define PTRDIFF_TYPE "int"
@ -1169,9 +1161,6 @@ enum data_align { align_abi, align_opt, align_both };
#define INT_REGNO_P(N) \ #define INT_REGNO_P(N) \
((N) <= 31 || (N) == ARG_POINTER_REGNUM || (N) == FRAME_POINTER_REGNUM) ((N) <= 31 || (N) == ARG_POINTER_REGNUM || (N) == FRAME_POINTER_REGNUM)
/* PAIRED SIMD registers are just the FPRs. */
#define PAIRED_SIMD_REGNO_P(N) ((N) >= 32 && (N) <= 63)
/* True if register is the CA register. */ /* True if register is the CA register. */
#define CA_REGNO_P(N) ((N) == CA_REGNO) #define CA_REGNO_P(N) ((N) == CA_REGNO)
@ -1232,9 +1221,6 @@ enum data_align { align_abi, align_opt, align_both };
(ALTIVEC_VECTOR_MODE (MODE) || VSX_VECTOR_MODE (MODE) \ (ALTIVEC_VECTOR_MODE (MODE) || VSX_VECTOR_MODE (MODE) \
|| (MODE) == V2DImode || (MODE) == V1TImode) || (MODE) == V2DImode || (MODE) == V1TImode)
#define PAIRED_VECTOR_MODE(MODE) \
((MODE) == V2SFmode)
/* Post-reload, we can't use any new AltiVec registers, as we already /* Post-reload, we can't use any new AltiVec registers, as we already
emitted the vrsave mask. */ emitted the vrsave mask. */
@ -2484,8 +2470,8 @@ extern int frame_pointer_needed;
#define RS6000_BTC_SAT RS6000_BTC_MISC /* saturate sets VSCR. */ #define RS6000_BTC_SAT RS6000_BTC_MISC /* saturate sets VSCR. */
/* Builtin targets. For now, we reuse the masks for those options that are in /* Builtin targets. For now, we reuse the masks for those options that are in
target flags, and pick two random bits for paired and ldbl128, which target flags, and pick a random bit for ldbl128, which isn't in
aren't in target_flags. */ target_flags. */
#define RS6000_BTM_ALWAYS 0 /* Always enabled. */ #define RS6000_BTM_ALWAYS 0 /* Always enabled. */
#define RS6000_BTM_ALTIVEC MASK_ALTIVEC /* VMX/altivec vectors. */ #define RS6000_BTM_ALTIVEC MASK_ALTIVEC /* VMX/altivec vectors. */
#define RS6000_BTM_CMPB MASK_CMPB /* ISA 2.05: compare bytes. */ #define RS6000_BTM_CMPB MASK_CMPB /* ISA 2.05: compare bytes. */
@ -2495,7 +2481,6 @@ extern int frame_pointer_needed;
#define RS6000_BTM_P9_MISC MASK_P9_MISC /* ISA 3.0 misc. non-vector */ #define RS6000_BTM_P9_MISC MASK_P9_MISC /* ISA 3.0 misc. non-vector */
#define RS6000_BTM_CRYPTO MASK_CRYPTO /* crypto funcs. */ #define RS6000_BTM_CRYPTO MASK_CRYPTO /* crypto funcs. */
#define RS6000_BTM_HTM MASK_HTM /* hardware TM funcs. */ #define RS6000_BTM_HTM MASK_HTM /* hardware TM funcs. */
#define RS6000_BTM_PAIRED MASK_MULHW /* 750CL paired insns. */
#define RS6000_BTM_FRE MASK_POPCNTB /* FRE instruction. */ #define RS6000_BTM_FRE MASK_POPCNTB /* FRE instruction. */
#define RS6000_BTM_FRES MASK_PPC_GFXOPT /* FRES instruction. */ #define RS6000_BTM_FRES MASK_PPC_GFXOPT /* FRES instruction. */
#define RS6000_BTM_FRSQRTE MASK_PPC_GFXOPT /* FRSQRTE instruction. */ #define RS6000_BTM_FRSQRTE MASK_PPC_GFXOPT /* FRSQRTE instruction. */
@ -2541,7 +2526,6 @@ extern int frame_pointer_needed;
#undef RS6000_BUILTIN_D #undef RS6000_BUILTIN_D
#undef RS6000_BUILTIN_H #undef RS6000_BUILTIN_H
#undef RS6000_BUILTIN_P #undef RS6000_BUILTIN_P
#undef RS6000_BUILTIN_Q
#undef RS6000_BUILTIN_X #undef RS6000_BUILTIN_X
#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) ENUM, #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
@ -2552,7 +2536,6 @@ extern int frame_pointer_needed;
#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) ENUM, #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) ENUM, #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) ENUM, #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
#define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) ENUM, #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
enum rs6000_builtins enum rs6000_builtins
@ -2570,20 +2553,14 @@ enum rs6000_builtins
#undef RS6000_BUILTIN_D #undef RS6000_BUILTIN_D
#undef RS6000_BUILTIN_H #undef RS6000_BUILTIN_H
#undef RS6000_BUILTIN_P #undef RS6000_BUILTIN_P
#undef RS6000_BUILTIN_Q
#undef RS6000_BUILTIN_X #undef RS6000_BUILTIN_X
enum rs6000_builtin_type_index enum rs6000_builtin_type_index
{ {
RS6000_BTI_NOT_OPAQUE, RS6000_BTI_NOT_OPAQUE,
RS6000_BTI_opaque_V2SI,
RS6000_BTI_opaque_V2SF,
RS6000_BTI_opaque_p_V2SI,
RS6000_BTI_opaque_V4SI, RS6000_BTI_opaque_V4SI,
RS6000_BTI_V16QI, /* __vector signed char */ RS6000_BTI_V16QI, /* __vector signed char */
RS6000_BTI_V1TI, RS6000_BTI_V1TI,
RS6000_BTI_V2SI,
RS6000_BTI_V2SF,
RS6000_BTI_V2DI, RS6000_BTI_V2DI,
RS6000_BTI_V2DF, RS6000_BTI_V2DF,
RS6000_BTI_V4HI, RS6000_BTI_V4HI,
@ -2638,16 +2615,11 @@ enum rs6000_builtin_type_index
}; };
#define opaque_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V2SI])
#define opaque_V2SF_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V2SF])
#define opaque_p_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_p_V2SI])
#define opaque_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V4SI]) #define opaque_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V4SI])
#define V16QI_type_node (rs6000_builtin_types[RS6000_BTI_V16QI]) #define V16QI_type_node (rs6000_builtin_types[RS6000_BTI_V16QI])
#define V1TI_type_node (rs6000_builtin_types[RS6000_BTI_V1TI]) #define V1TI_type_node (rs6000_builtin_types[RS6000_BTI_V1TI])
#define V2DI_type_node (rs6000_builtin_types[RS6000_BTI_V2DI]) #define V2DI_type_node (rs6000_builtin_types[RS6000_BTI_V2DI])
#define V2DF_type_node (rs6000_builtin_types[RS6000_BTI_V2DF]) #define V2DF_type_node (rs6000_builtin_types[RS6000_BTI_V2DF])
#define V2SI_type_node (rs6000_builtin_types[RS6000_BTI_V2SI])
#define V2SF_type_node (rs6000_builtin_types[RS6000_BTI_V2SF])
#define V4HI_type_node (rs6000_builtin_types[RS6000_BTI_V4HI]) #define V4HI_type_node (rs6000_builtin_types[RS6000_BTI_V4HI])
#define V4SI_type_node (rs6000_builtin_types[RS6000_BTI_V4SI]) #define V4SI_type_node (rs6000_builtin_types[RS6000_BTI_V4SI])
#define V4SF_type_node (rs6000_builtin_types[RS6000_BTI_V4SF]) #define V4SF_type_node (rs6000_builtin_types[RS6000_BTI_V4SF])

12
gcc/config/rs6000/rs6000.md
View File

@ -394,7 +394,6 @@
(SF "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT") (SF "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT")
(DF "(TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) (DF "(TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
|| VECTOR_UNIT_VSX_P (DFmode)") || VECTOR_UNIT_VSX_P (DFmode)")
(V2SF "TARGET_PAIRED_FLOAT")
(V4SF "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)") (V4SF "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)")
(V2DF "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V2DFmode)") (V2DF "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V2DFmode)")
(KF "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (KFmode)") (KF "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (KFmode)")
@ -11663,16 +11662,6 @@
(const_string "mfcr"))) (const_string "mfcr")))
(set_attr "length" "8")]) (set_attr "length" "8")])
;; Same as above, but get the OV/ORDERED bit.
(define_insn "move_from_CR_ov_bit"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(unspec:SI [(match_operand:CC 1 "cc_reg_operand" "y")]
UNSPEC_MV_CR_OV))]
"TARGET_PAIRED_FLOAT"
"mfcr %0\;rlwinm %0,%0,%t1,1"
[(set_attr "type" "mfcr")
(set_attr "length" "8")])
(define_insn "" (define_insn ""
[(set (match_operand:DI 0 "gpc_reg_operand" "=r") [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
(match_operator:DI 1 "scc_comparison_operator" (match_operator:DI 1 "scc_comparison_operator"
@ -14572,6 +14561,5 @@
(include "vsx.md") (include "vsx.md")
(include "altivec.md") (include "altivec.md")
(include "dfp.md") (include "dfp.md")
(include "paired.md")
(include "crypto.md") (include "crypto.md")
(include "htm.md") (include "htm.md")

4
gcc/config/rs6000/rs6000.opt
View File

@ -357,10 +357,6 @@ misel=yes
Target RejectNegative Alias(misel) Warn(%<-misel=yes%> is deprecated; use %<-misel%> instead) Target RejectNegative Alias(misel) Warn(%<-misel=yes%> is deprecated; use %<-misel%> instead)
Deprecated option. Use -misel instead. Deprecated option. Use -misel instead.
mpaired
Target Var(rs6000_paired_float) Save
Generate PPC750CL paired-single instructions.
mdebug= mdebug=
Target RejectNegative Joined Target RejectNegative Joined
-mdebug= Enable debug output. -mdebug= Enable debug output.

3
gcc/config/rs6000/t-rs6000
View File

@ -72,5 +72,4 @@ MD_INCLUDES = $(srcdir)/config/rs6000/rs64.md \
$(srcdir)/config/rs6000/altivec.md \ $(srcdir)/config/rs6000/altivec.md \
$(srcdir)/config/rs6000/crypto.md \ $(srcdir)/config/rs6000/crypto.md \
$(srcdir)/config/rs6000/htm.md \ $(srcdir)/config/rs6000/htm.md \
$(srcdir)/config/rs6000/dfp.md \ $(srcdir)/config/rs6000/dfp.md
$(srcdir)/config/rs6000/paired.md

8
gcc/doc/invoke.texi
View File

@ -1089,7 +1089,6 @@ See RS/6000 and PowerPC Options.
-mstring-compare-inline-limit=@var{num} @gol -mstring-compare-inline-limit=@var{num} @gol
-misel -mno-isel @gol -misel -mno-isel @gol
-misel=yes -misel=no @gol -misel=yes -misel=no @gol
-mpaired @gol
-mvrsave -mno-vrsave @gol -mvrsave -mno-vrsave @gol
-mmulhw -mno-mulhw @gol -mmulhw -mno-mulhw @gol
-mdlmzb -mno-dlmzb @gol -mdlmzb -mno-dlmzb @gol
@ -23475,13 +23474,6 @@ This switch enables or disables the generation of ISEL instructions.
This switch has been deprecated. Use @option{-misel} and This switch has been deprecated. Use @option{-misel} and
@option{-mno-isel} instead. @option{-mno-isel} instead.
@item -mpaired
@itemx -mno-paired
@opindex mpaired
@opindex mno-paired
This switch enables or disables the generation of PAIRED simd
instructions.
@item -mvsx @item -mvsx
@itemx -mno-vsx @itemx -mno-vsx
@opindex mvsx @opindex mvsx