mirror of git://gcc.gnu.org/git/gcc.git
re PR target/70525 (generating 'vpandn' without the mode suffix, gnu as fails to assemble (-mavx512bw))
PR target/70525 * config/i386/sse.md (*andnot<mode>3): Simplify assertions. Use vpandn<ssemodesuffix> for V16SI/V8DImode, vpandnq for V32HI/V64QImode, don't use <mask_operand3_1>, fix up formatting. (*andnot<mode>3_mask): Remove insn with VI12_AVX512VL iterator. * gcc.target/i386/pr70525.c: New test. From-SVN: r234739
This commit is contained in:
Jakub Jelinek
parent
62b233f224
commit
55fc79b2a6
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@ -1,3 +1,11 @@
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2016-04-05 Jakub Jelinek <jakub@redhat.com>
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PR target/70525
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* config/i386/sse.md (*andnot<mode>3): Simplify assertions.
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Use vpandn<ssemodesuffix> for V16SI/V8DImode, vpandnq for
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V32HI/V64QImode, don't use <mask_operand3_1>, fix up formatting.
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(*andnot<mode>3_mask): Remove insn with VI12_AVX512VL iterator.
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2016-04-05 Richard Biener <rguenther@suse.de>
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PR middle-end/70499
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@ -9,7 +17,7 @@
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PR ipa/66223
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* ipa-devirt.c (maybe_record_node): Do not optimize cxa_pure_virtual
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calls when sanitizing.
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(possible_polymorphic_call_target_p)" FIx formating.
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(possible_polymorphic_call_target_p): Fix formating.
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2016-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
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Jakub Jelinek <jakub@redhat.com>
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@ -11377,45 +11377,46 @@
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case MODE_XI:
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gcc_assert (TARGET_AVX512F);
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case MODE_OI:
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gcc_assert (TARGET_AVX2 || TARGET_AVX512VL);
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gcc_assert (TARGET_AVX2);
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case MODE_TI:
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gcc_assert (TARGET_SSE2 || TARGET_AVX512VL);
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gcc_assert (TARGET_SSE2);
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switch (<MODE>mode)
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{
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case V16SImode:
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case V8DImode:
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if (TARGET_AVX512F)
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{
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tmp = "pandn<ssemodesuffix>";
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break;
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}
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case V8SImode:
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case V4DImode:
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case V4SImode:
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case V2DImode:
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if (TARGET_AVX512VL)
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{
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tmp = "pandn<ssemodesuffix>";
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break;
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}
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default:
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tmp = TARGET_AVX512VL ? "pandnq" : "pandn";
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}
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{
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case V64QImode:
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case V32HImode:
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/* There is no vpandnb or vpandnw instruction, nor vpandn for
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512-bit vectors. Use vpandnq instead. */
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tmp = "pandnq";
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break;
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case V16SImode:
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case V8DImode:
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tmp = "pandn<ssemodesuffix>";
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break;
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case V8SImode:
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case V4DImode:
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case V4SImode:
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case V2DImode:
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tmp = TARGET_AVX512VL ? "pandn<ssemodesuffix>" : "pandn";
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break;
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default:
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tmp = TARGET_AVX512VL ? "pandnq" : "pandn";
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break;
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}
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break;
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case MODE_V16SF:
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case MODE_V16SF:
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gcc_assert (TARGET_AVX512F);
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case MODE_V8SF:
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case MODE_V8SF:
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gcc_assert (TARGET_AVX);
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case MODE_V4SF:
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case MODE_V4SF:
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gcc_assert (TARGET_SSE);
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tmp = "andnps";
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break;
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default:
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default:
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gcc_unreachable ();
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}
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}
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switch (which_alternative)
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{
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@ -11423,7 +11424,7 @@
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ops = "%s\t{%%2, %%0|%%0, %%2}";
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break;
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case 1:
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ops = "v%s\t{%%2, %%1, %%0<mask_operand3_1>|%%0<mask_operand3_1>, %%1, %%2}";
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ops = "v%s\t{%%2, %%1, %%0|%%0, %%1, %%2}";
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break;
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default:
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gcc_unreachable ();
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@ -11473,21 +11474,6 @@
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(set_attr "prefix" "evex")
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(set_attr "mode" "<sseinsnmode>")])
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(define_insn "*andnot<mode>3_mask"
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[(set (match_operand:VI12_AVX512VL 0 "register_operand" "=v")
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(vec_merge:VI12_AVX512VL
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(and:VI12_AVX512VL
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(not:VI12_AVX512VL
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(match_operand:VI12_AVX512VL 1 "register_operand" "v"))
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(match_operand:VI12_AVX512VL 2 "nonimmediate_operand" "vm"))
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(match_operand:VI12_AVX512VL 3 "vector_move_operand" "0C")
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(match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))]
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"TARGET_AVX512BW"
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"vpandn<ssemodesuffix>\t{%2, %1, %0%{%4%}%N3|%0%{%4%}%N3, %1, %2}";
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[(set_attr "type" "sselog")
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(set_attr "prefix" "evex")
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(set_attr "mode" "<sseinsnmode>")])
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(define_expand "<code><mode>3"
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[(set (match_operand:VI 0 "register_operand")
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(any_logic:VI
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@ -1,3 +1,8 @@
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2016-04-05 Jakub Jelinek <jakub@redhat.com>
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PR target/70525
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* gcc.target/i386/pr70525.c: New test.
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2016-04-05 Richard Biener <rguenther@suse.de>
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PR middle-end/70499
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@ -0,0 +1,32 @@
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/* PR target/70525 */
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/* { dg-do assemble { target avx512bw } } */
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/* { dg-options "-O2 -mavx512bw -mno-avx512vl" } */
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typedef char v64qi __attribute__ ((vector_size (64)));
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typedef short v32hi __attribute__ ((vector_size (64)));
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typedef int v16si __attribute__ ((vector_size (64)));
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typedef long long v8di __attribute__ ((vector_size (64)));
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v64qi
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f1 (v64qi x, v64qi y)
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{
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return x & ~y;
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}
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v32hi
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f2 (v32hi x, v32hi y)
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{
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return x & ~y;
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}
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v16si
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f3 (v16si x, v16si y)
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{
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return x & ~y;
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}
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v8di
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f4 (v8di x, v8di y)
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{
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return x & ~y;
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}
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