mirror of git://gcc.gnu.org/git/gcc.git
Charles Hannum
parent
8763cbe838
commit
581cc66cd5
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/* Subroutines for insn-output.c for SPUR. Adapted from routines for
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the Motorola 68000 family.
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Copyright (C) 1988, 1991 Free Software Foundation, Inc.
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This file is part of GNU CC.
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GNU CC is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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GNU CC is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with GNU CC; see the file COPYING. If not, write to
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the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
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#include "config.h"
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#include "rtl.h"
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#include "regs.h"
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#include "hard-reg-set.h"
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#include "real.h"
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#include "insn-config.h"
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#include "conditions.h"
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#include "insn-flags.h"
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#include "output.h"
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#include "insn-attr.h"
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static rtx find_addr_reg ();
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char *
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output_compare (operands, opcode, exchange_opcode,
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neg_opcode, neg_exchange_opcode)
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rtx *operands;
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char *opcode;
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char *exchange_opcode;
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char *neg_opcode;
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char *neg_exchange_opcode;
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{
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static char buf[100];
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operands[2] = operands[0];
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if (GET_CODE (cc_prev_status.value1) == CONST_INT)
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{
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operands[1] = cc_prev_status.value1;
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operands[0] = cc_prev_status.value2;
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opcode = exchange_opcode, neg_opcode = neg_exchange_opcode;
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}
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else
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{
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operands[0] = cc_prev_status.value1;
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operands[1] = cc_prev_status.value2;
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}
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if (TARGET_LONG_JUMPS)
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sprintf (buf,
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"cmp_br_delayed %s,%%0,%%1,1f\n\tnop\n\tjump %%l2\n\tnop\n1:",
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neg_opcode);
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else
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sprintf (buf, "cmp_br_delayed %s,%%0,%%1,%%l2\n\tnop", opcode);
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return buf;
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}
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/* Return the best assembler insn template
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for moving operands[1] into operands[0] as a fullword. */
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static char *
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singlemove_string (operands)
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rtx *operands;
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{
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if (GET_CODE (operands[0]) == MEM)
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return "st_32 %r1,%0";
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if (GET_CODE (operands[1]) == MEM)
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return "ld_32 %0,%1\n\tnop";
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if (GET_CODE (operands[1]) == REG)
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return "add_nt %0,%1,$0";
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return "add_nt %0,r0,%1";
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}
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/* Output assembler code to perform a doubleword move insn
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with operands OPERANDS. */
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char *
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output_move_double (operands)
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rtx *operands;
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{
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enum { REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP } optype0, optype1;
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rtx latehalf[2];
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rtx addreg0 = 0, addreg1 = 0;
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/* First classify both operands. */
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if (REG_P (operands[0]))
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optype0 = REGOP;
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else if (offsettable_memref_p (operands[0]))
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optype0 = OFFSOP;
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else if (GET_CODE (operands[0]) == MEM)
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optype0 = MEMOP;
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else
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optype0 = RNDOP;
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if (REG_P (operands[1]))
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optype1 = REGOP;
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else if (CONSTANT_P (operands[1]))
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optype1 = CNSTOP;
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else if (offsettable_memref_p (operands[1]))
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optype1 = OFFSOP;
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else if (GET_CODE (operands[1]) == MEM)
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optype1 = MEMOP;
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else
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optype1 = RNDOP;
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/* Check for the cases that the operand constraints are not
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supposed to allow to happen. Abort if we get one,
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because generating code for these cases is painful. */
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if (optype0 == RNDOP || optype1 == RNDOP)
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abort ();
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/* If an operand is an unoffsettable memory ref, find a register
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we can increment temporarily to make it refer to the second word. */
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if (optype0 == MEMOP)
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addreg0 = find_addr_reg (XEXP (operands[0], 0));
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if (optype1 == MEMOP)
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addreg1 = find_addr_reg (XEXP (operands[1], 0));
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/* Ok, we can do one word at a time.
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Normally we do the low-numbered word first,
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but if either operand is autodecrementing then we
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do the high-numbered word first.
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In either case, set up in LATEHALF the operands to use
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for the high-numbered word and in some cases alter the
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operands in OPERANDS to be suitable for the low-numbered word. */
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if (optype0 == REGOP)
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latehalf[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
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else if (optype0 == OFFSOP)
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latehalf[0] = adj_offsettable_operand (operands[0], 4);
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else
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latehalf[0] = operands[0];
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if (optype1 == REGOP)
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latehalf[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
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else if (optype1 == OFFSOP)
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latehalf[1] = adj_offsettable_operand (operands[1], 4);
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else if (optype1 == CNSTOP)
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{
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if (GET_CODE (operands[1]) == CONST_DOUBLE)
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{
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latehalf[1] = gen_rtx (CONST_INT, VOIDmode,
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CONST_DOUBLE_HIGH (operands[1]));
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operands[1] = gen_rtx (CONST_INT, VOIDmode,
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CONST_DOUBLE_LOW (operands[1]));
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}
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else if (CONSTANT_P (operands[1]))
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latehalf[1] = const0_rtx;
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}
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else
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latehalf[1] = operands[1];
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/* If the first move would clobber the source of the second one,
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do them in the other order. This happens only for registers;
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such overlap can't happen in memory unless the user explicitly
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sets it up, and that is an undefined circumstance. */
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if (optype0 == REGOP && optype1 == REGOP
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&& REGNO (operands[0]) == REGNO (latehalf[1]))
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{
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/* Make any unoffsettable addresses point at high-numbered word. */
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if (addreg0)
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output_asm_insn ("add_nt %0,%0,$4", &addreg0);
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if (addreg1)
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output_asm_insn ("add_nt %0,%0,$4", &addreg1);
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/* Do that word. */
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output_asm_insn (singlemove_string (latehalf), latehalf);
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/* Undo the adds we just did. */
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if (addreg0)
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output_asm_insn ("add_nt %0,%0,$-4", &addreg0);
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if (addreg1)
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output_asm_insn ("add_nt %0,%0,$-4", &addreg0);
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/* Do low-numbered word. */
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return singlemove_string (operands);
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}
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/* Normal case: do the two words, low-numbered first. */
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output_asm_insn (singlemove_string (operands), operands);
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/* Make any unoffsettable addresses point at high-numbered word. */
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if (addreg0)
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output_asm_insn ("add_nt %0,%0,$4", &addreg0);
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if (addreg1)
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output_asm_insn ("add_nt %0,%0,$4", &addreg1);
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/* Do that word. */
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output_asm_insn (singlemove_string (latehalf), latehalf);
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/* Undo the adds we just did. */
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if (addreg0)
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output_asm_insn ("add_nt %0,%0,$-4", &addreg0);
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if (addreg1)
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output_asm_insn ("add_nt %0,%0,$-4", &addreg1);
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return "";
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}
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static char *
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output_fp_move_double (operands)
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rtx *operands;
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{
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if (FP_REG_P (operands[0]))
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{
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if (FP_REG_P (operands[1]))
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return "fmov %0,%1";
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if (GET_CODE (operands[1]) == REG)
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{
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rtx xoperands[2];
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int offset = - get_frame_size () - 8;
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xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
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xoperands[0] = gen_rtx (CONST_INT, VOIDmode, offset + 4);
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output_asm_insn ("st_32 %1,r25,%0", xoperands);
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xoperands[1] = operands[1];
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xoperands[0] = gen_rtx (CONST_INT, VOIDmode, offset);
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output_asm_insn ("st_32 %1,r25,%0", xoperands);
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xoperands[1] = operands[0];
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output_asm_insn ("ld_dbl %1,r25,%0\n\tnop", xoperands);
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return "";
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}
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return "ld_dbl %0,%1\n\tnop";
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}
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else if (FP_REG_P (operands[1]))
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{
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if (GET_CODE (operands[0]) == REG)
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{
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rtx xoperands[2];
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int offset = - get_frame_size () - 8;
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xoperands[0] = gen_rtx (CONST_INT, VOIDmode, offset);
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xoperands[1] = operands[1];
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output_asm_insn ("st_dbl %1,r25,%0", xoperands);
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xoperands[1] = operands[0];
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output_asm_insn ("ld_32 %1,r25,%0\n\tnop", xoperands);
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xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
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xoperands[0] = gen_rtx (CONST_INT, VOIDmode, offset + 4);
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output_asm_insn ("ld_32 %1,r25,%0\n\tnop", xoperands);
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return "";
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}
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return "st_dbl %1,%0";
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}
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}
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/* Return a REG that occurs in ADDR with coefficient 1.
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ADDR can be effectively incremented by incrementing REG. */
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static rtx
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find_addr_reg (addr)
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rtx addr;
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{
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while (GET_CODE (addr) == PLUS)
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{
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if (GET_CODE (XEXP (addr, 0)) == REG)
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addr = XEXP (addr, 0);
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else if (GET_CODE (XEXP (addr, 1)) == REG)
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addr = XEXP (addr, 1);
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else if (CONSTANT_P (XEXP (addr, 0)))
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addr = XEXP (addr, 1);
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else if (CONSTANT_P (XEXP (addr, 1)))
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addr = XEXP (addr, 0);
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else
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abort ();
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}
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if (GET_CODE (addr) == REG)
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return addr;
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abort ();
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}
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/* Generate code to add a large integer constant to register, reg, storing
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* the result in a register, target. Offset must be 27-bit signed quantity */
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static char *
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output_add_large_offset (target, reg, offset)
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rtx target, reg;
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int offset;
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{
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rtx operands[3];
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int high, n, i;
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operands[0] = target, operands[1] = reg;
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for (high = offset, n = 0;
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(unsigned) (high + 0x2000) >= 0x4000;
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high >>= 1, n += 1)
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;
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operands[2] = gen_rtx (CONST_INT, VOIDmode, high);
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output_asm_insn ("add_nt r2,r0,%2", operands);
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i = n;
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while (i >= 3)
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output_asm_insn ("sll r2,r2,$3", operands), i -= 3;
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if (i == 2)
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output_asm_insn ("sll r2,r2,$2", operands);
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else if (i == 1)
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output_asm_insn ("sll r2,r2,$1", operands);
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output_asm_insn ("add_nt %0,r2,%1", operands);
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if (offset - (high << n) != 0)
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{
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operands[2] = gen_rtx (CONST_INT, VOIDmode, offset - (high << n));
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output_asm_insn ("add_nt %0,%0,%2", operands);
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}
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return "";
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}
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/* Additional TESTFN for matching. Like immediate_operand, but matches big
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* constants */
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int
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big_immediate_operand (op, mode)
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rtx op;
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enum machine_mode mode;
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{
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return (GET_CODE (op) == CONST_INT);
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}
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Reference in New Issue