mirror of git://gcc.gnu.org/git/gcc.git
re PR target/84431 (Suboptimal code for masked shifts (x86/x86-64))
PR target/84431 * config/i386/i386.md (*ashl<dwi>3_doubleword_mask): New pattern. (*ashl<dwi>3_doubleword_mask_1): Ditto. (*<shift_insn><dwi>3_doubleword_mask): Ditto. (*<shift_insn><dwi>3_doubleword_mask_1): Ditto. testsuite/ChangeLog: PR target/84431 * gcc.target/i386/pr84431.c: New test. From-SVN: r259739
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Uros Bizjak
Uros Bizjak
parent
782e476490
commit
6754dfa237
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@ -1,3 +1,11 @@
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2018-04-28 Uros Bizjak <ubizjak@gmail.com>
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PR target/84431
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* config/i386/i386.md (*ashl<dwi>3_doubleword_mask): New pattern.
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(*ashl<dwi>3_doubleword_mask_1): Ditto.
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(*<shift_insn><dwi>3_doubleword_mask): Ditto.
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(*<shift_insn><dwi>3_doubleword_mask_1): Ditto.
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2018-04-28 Richard Biener <rguenther@suse.de>
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* tree-cfg.c (verify_gimple_phi): Take a gphi * argument.
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@ -10357,6 +10357,77 @@
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""
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"ix86_expand_binary_operator (ASHIFT, <MODE>mode, operands); DONE;")
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(define_insn_and_split "*ashl<dwi>3_doubleword_mask"
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[(set (match_operand:<DWI> 0 "register_operand")
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(ashift:<DWI>
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(match_operand:<DWI> 1 "register_operand")
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(subreg:QI
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(and:SI
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(match_operand:SI 2 "register_operand" "c")
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(match_operand:SI 3 "const_int_operand")) 0)))
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(clobber (reg:CC FLAGS_REG))]
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"INTVAL (operands[3]) <= (<MODE_SIZE> * BITS_PER_UNIT)-1
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&& can_create_pseudo_p ()"
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"#"
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"&& 1"
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[(parallel
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[(set (match_dup 6)
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(ior:DWIH (ashift:DWIH (match_dup 6) (match_dup 2))
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(lshiftrt:DWIH (match_dup 5)
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(minus:QI (match_dup 8) (match_dup 2)))))
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(clobber (reg:CC FLAGS_REG))])
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(parallel
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[(set (match_dup 4)
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(ashift:DWIH (match_dup 5) (match_dup 2)))
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(clobber (reg:CC FLAGS_REG))])]
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{
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split_double_mode (<DWI>mode, &operands[0], 2, &operands[4], &operands[6]);
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operands[8] = GEN_INT (<MODE_SIZE> * BITS_PER_UNIT);
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if (INTVAL (operands[3]) < (<MODE_SIZE> * BITS_PER_UNIT)-1)
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emit_insn (gen_andsi3 (operands[2], operands[2], operands[3]));
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operands[2] = gen_lowpart (QImode, operands[2]);
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if (!rtx_equal_p (operands[6], operands[7]))
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emit_move_insn (operands[6], operands[7]);
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})
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(define_insn_and_split "*ashl<dwi>3_doubleword_mask_1"
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[(set (match_operand:<DWI> 0 "register_operand")
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(ashift:<DWI>
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(match_operand:<DWI> 1 "register_operand")
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(and:QI
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(match_operand:QI 2 "register_operand" "c")
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(match_operand:QI 3 "const_int_operand"))))
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(clobber (reg:CC FLAGS_REG))]
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"INTVAL (operands[3]) <= (<MODE_SIZE> * BITS_PER_UNIT)-1
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&& can_create_pseudo_p ()"
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"#"
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"&& 1"
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[(parallel
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[(set (match_dup 6)
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(ior:DWIH (ashift:DWIH (match_dup 6) (match_dup 2))
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(lshiftrt:DWIH (match_dup 5)
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(minus:QI (match_dup 8) (match_dup 2)))))
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(clobber (reg:CC FLAGS_REG))])
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(parallel
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[(set (match_dup 4)
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(ashift:DWIH (match_dup 5) (match_dup 2)))
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(clobber (reg:CC FLAGS_REG))])]
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{
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split_double_mode (<DWI>mode, &operands[0], 2, &operands[4], &operands[6]);
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operands[8] = GEN_INT (<MODE_SIZE> * BITS_PER_UNIT);
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if (INTVAL (operands[3]) < (<MODE_SIZE> * BITS_PER_UNIT)-1)
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emit_insn (gen_andqi3 (operands[2], operands[2], operands[3]));
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if (!rtx_equal_p (operands[6], operands[7]))
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emit_move_insn (operands[6], operands[7]);
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})
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(define_insn "*ashl<mode>3_doubleword"
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[(set (match_operand:DWI 0 "register_operand" "=&r")
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(ashift:DWI (match_operand:DWI 1 "reg_or_pm1_operand" "0n")
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@ -11038,6 +11109,77 @@
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""
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[(set_attr "isa" "*,bmi2")])
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(define_insn_and_split "*<shift_insn><dwi>3_doubleword_mask"
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[(set (match_operand:<DWI> 0 "register_operand")
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(any_shiftrt:<DWI>
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(match_operand:<DWI> 1 "register_operand")
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(subreg:QI
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(and:SI
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(match_operand:SI 2 "register_operand" "c")
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(match_operand:SI 3 "const_int_operand")) 0)))
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(clobber (reg:CC FLAGS_REG))]
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"INTVAL (operands[3]) <= (<MODE_SIZE> * BITS_PER_UNIT)-1
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&& can_create_pseudo_p ()"
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"#"
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"&& 1"
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[(parallel
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[(set (match_dup 4)
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(ior:DWIH (lshiftrt:DWIH (match_dup 4) (match_dup 2))
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(ashift:DWIH (match_dup 7)
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(minus:QI (match_dup 8) (match_dup 2)))))
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(clobber (reg:CC FLAGS_REG))])
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(parallel
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[(set (match_dup 6)
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(any_shiftrt:DWIH (match_dup 7) (match_dup 2)))
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(clobber (reg:CC FLAGS_REG))])]
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{
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split_double_mode (<DWI>mode, &operands[0], 2, &operands[4], &operands[6]);
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operands[8] = GEN_INT (<MODE_SIZE> * BITS_PER_UNIT);
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if (INTVAL (operands[3]) < (<MODE_SIZE> * BITS_PER_UNIT)-1)
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emit_insn (gen_andsi3 (operands[2], operands[2], operands[3]));
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operands[2] = gen_lowpart (QImode, operands[2]);
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if (!rtx_equal_p (operands[4], operands[5]))
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emit_move_insn (operands[4], operands[5]);
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})
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(define_insn_and_split "*<shift_insn><dwi>3_doubleword_mask_1"
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[(set (match_operand:<DWI> 0 "register_operand")
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(any_shiftrt:<DWI>
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(match_operand:<DWI> 1 "register_operand")
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(and:QI
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(match_operand:QI 2 "register_operand" "c")
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(match_operand:QI 3 "const_int_operand"))))
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(clobber (reg:CC FLAGS_REG))]
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"INTVAL (operands[3]) <= (<MODE_SIZE> * BITS_PER_UNIT)-1
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&& can_create_pseudo_p ()"
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"#"
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"&& 1"
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[(parallel
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[(set (match_dup 4)
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(ior:DWIH (lshiftrt:DWIH (match_dup 4) (match_dup 2))
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(ashift:DWIH (match_dup 7)
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(minus:QI (match_dup 8) (match_dup 2)))))
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(clobber (reg:CC FLAGS_REG))])
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(parallel
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[(set (match_dup 6)
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(any_shiftrt:DWIH (match_dup 7) (match_dup 2)))
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(clobber (reg:CC FLAGS_REG))])]
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{
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split_double_mode (<DWI>mode, &operands[0], 2, &operands[4], &operands[6]);
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operands[8] = GEN_INT (<MODE_SIZE> * BITS_PER_UNIT);
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if (INTVAL (operands[3]) < (<MODE_SIZE> * BITS_PER_UNIT)-1)
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emit_insn (gen_andqi3 (operands[2], operands[2], operands[3]));
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if (!rtx_equal_p (operands[4], operands[5]))
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emit_move_insn (operands[4], operands[5]);
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})
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(define_insn_and_split "*<shift_insn><mode>3_doubleword"
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[(set (match_operand:DWI 0 "register_operand" "=&r")
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(any_shiftrt:DWI (match_operand:DWI 1 "register_operand" "0")
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@ -1,3 +1,8 @@
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2018-04-28 Uros Bizjak <ubizjak@gmail.com>
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PR target/84431
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* gcc.target/i386/pr84431.c: New test.
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2018-04-27 Martin Jambor <mjambor@suse.cz>
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PR ipa/85549
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@ -0,0 +1,19 @@
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/* PR target/84431 */
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/* { dg-do compile } */
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/* { dg-options "-O2" } */
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#ifdef __SIZEOF_INT128__
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typedef unsigned __int128 U;
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typedef signed __int128 S;
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# define M 63
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#else
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typedef unsigned long long U;
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typedef signed long long S;
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# define M 31
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#endif
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S f1 (S a, int s) { return a >> (s & M); }
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U f2 (U a, int s) { return a >> (s & M); }
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U f3 (U a, int s) { return a << (s & M); }
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/* { dg-final { scan-assembler-not "and" } } */
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