mirror of git://gcc.gnu.org/git/gcc.git
[AArch64] Split X-reg UBFIZ into W-reg LSL when possible
* config/aarch64/aarch64.md: New define_split above bswap<mode>2. * gcc.target/aarch64/ubfiz_lsl_1.c: New test. From-SVN: r243756
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2016-12-16 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
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* config/aarch64/aarch64.md: New define_split above bswap<mode>2.
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2016-12-16 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
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* config/aarch64/aarch64.md: New define_split above insv<mode>.
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@ -4439,6 +4439,24 @@
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[(set_attr "type" "bfx")]
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)
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;; When the bit position and width of the equivalent extraction add up to 32
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;; we can use a W-reg LSL instruction taking advantage of the implicit
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;; zero-extension of the X-reg.
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(define_split
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[(set (match_operand:DI 0 "register_operand")
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(and:DI (ashift:DI (match_operand:DI 1 "register_operand")
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(match_operand 2 "const_int_operand"))
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(match_operand 3 "const_int_operand")))]
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"aarch64_mask_and_shift_for_ubfiz_p (DImode, operands[3], operands[2])
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&& (INTVAL (operands[2]) + popcount_hwi (INTVAL (operands[3])))
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== GET_MODE_BITSIZE (SImode)"
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[(set (match_dup 0)
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(zero_extend:DI (ashift:SI (match_dup 4) (match_dup 2))))]
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{
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operands[4] = gen_lowpart (SImode, operands[1]);
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}
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)
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(define_insn "bswap<mode>2"
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[(set (match_operand:GPI 0 "register_operand" "=r")
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(bswap:GPI (match_operand:GPI 1 "register_operand" "r")))]
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@ -1,3 +1,7 @@
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2016-12-16 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
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* gcc.target/aarch64/ubfiz_lsl_1.c: New test.
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2016-12-16 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
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* gcc.target/aarch64/ubfx_lsr_1.c: New test.
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@ -0,0 +1,13 @@
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/* { dg-do compile } */
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/* { dg-options "-O2" } */
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/* Check that an X-reg UBFIZ can be simplified into a W-reg LSL. */
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long long
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f2 (long long x)
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{
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return (x << 5) & 0xffffffff;
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}
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/* { dg-final { scan-assembler "lsl\tw" } } */
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/* { dg-final { scan-assembler-not "ubfiz\tx" } } */
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