mirror of git://gcc.gnu.org/git/gcc.git
sh.md (*prefetch_i4, [...]): Merge into ...
* config/sh/sh.md (*prefetch_i4, prefetch_m2a): Merge into ... (*prefetch): ... this new insn. * gcc.target/sh/sh2a-prefetch.c: Rename to ... * gcc.target/sh/prefetch.c: ... this. Enable test case for m4*. From-SVN: r186225
This commit is contained in:
Oleg Endo
parent
5af6fa0b38
commit
6b45f126b1
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@ -1,3 +1,8 @@
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2012-04-08 Oleg Endo <olegendo@gcc.gnu.org>
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* config/sh/sh.md (*prefetch_i4, prefetch_m2a): Merge into ...
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(*prefetch): ... this new insn.
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2012-04-07 Oleg Endo <olegendo@gcc.gnu.org>
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* config/sh/sh.h (high_life_started): Remove
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@ -909,8 +909,10 @@
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(match_operand:DI 1 "arith_operand" "r"))
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(const_int 0)))]
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"TARGET_SH1"
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"* return output_branchy_insn (EQ, \"tst\\t%S1,%S0\;bf\\t%l9\;tst\\t%R1,%R0\",
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insn, operands);"
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{
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return output_branchy_insn (EQ, "tst\t%S1,%S0;bf\t%l9;tst\t%R1,%R0",
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insn, operands);
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}
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[(set_attr "length" "6")
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(set_attr "type" "arith3b")])
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@ -3156,7 +3158,6 @@ label:
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(and:SI (match_operand:SI 1 "logical_reg_operand" "")
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(match_operand:SI 2 "logical_operand" "")))]
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""
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"
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{
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if (TARGET_SH1
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&& CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 255)
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@ -3165,7 +3166,7 @@ label:
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gen_lowpart (QImode, operands[1])));
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DONE;
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}
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}")
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})
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(define_insn_and_split "anddi3"
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[(set (match_operand:DI 0 "arith_reg_dest" "=r,r,r")
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@ -3179,14 +3180,13 @@ label:
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"reload_completed
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&& ! logical_operand (operands[2], DImode)"
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[(const_int 0)]
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"
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{
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if ((unsigned)INTVAL (operands[2]) == (unsigned) 0xffffffff)
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emit_insn (gen_mshflo_l_di (operands[0], operands[1], CONST0_RTX (DImode)));
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else
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emit_insn (gen_mshfhi_l_di (operands[0], CONST0_RTX (DImode), operands[1]));
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DONE;
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}"
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}
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[(set_attr "type" "arith_media")])
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(define_insn "andcsi3"
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@ -5638,7 +5638,9 @@ label:
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"TARGET_SH1
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&& (arith_reg_operand (operands[0], DImode)
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|| arith_reg_operand (operands[1], DImode))"
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"* return output_movedouble (insn, operands, DImode);"
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{
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return output_movedouble (insn, operands, DImode);
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}
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[(set_attr "length" "4")
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(set_attr "type" "pcload,move,load,store,move,pcload,move,move")])
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@ -13559,14 +13561,6 @@ label:
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}
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[(set_attr "type" "other")])
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(define_insn "*prefetch_i4"
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[(prefetch (match_operand:SI 0 "register_operand" "r")
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(match_operand:SI 1 "const_int_operand" "n")
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(match_operand:SI 2 "const_int_operand" "n"))]
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"(TARGET_HARD_SH4 || TARGET_SHCOMPACT) && !TARGET_VXWORKS_RTP"
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"pref @%0";
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[(set_attr "type" "other")])
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;; In user mode, the "pref" instruction will raise a RADDERR exception
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;; for accesses to [0x80000000,0xffffffff]. This makes it an unsuitable
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;; implementation of __builtin_prefetch for VxWorks RTPs.
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@ -13585,12 +13579,12 @@ label:
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operands[0] = force_reg (Pmode, operands[0]);
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})
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(define_insn "prefetch_m2a"
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(define_insn "*prefetch"
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[(prefetch (match_operand:SI 0 "register_operand" "r")
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(match_operand:SI 1 "const_int_operand" "n")
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(match_operand:SI 2 "const_int_operand" "n"))]
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"TARGET_SH2A"
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"pref\\t@%0"
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"(TARGET_SH2A || TARGET_HARD_SH4 || TARGET_SHCOMPACT) && !TARGET_VXWORKS_RTP"
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"pref @%0"
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[(set_attr "type" "other")])
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(define_insn "alloco_i"
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@ -1,3 +1,8 @@
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2012-04-08 Oleg Endo <olegendo@gcc.gnu.org>
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* gcc.target/sh/sh2a-prefetch.c: Rename to ...
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* gcc.target/sh/prefetch.c: ... this. Enable test case for m4*.
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2012-04-08 Tobias Burnus <burnus@net-b.de>
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PR fortran/40973
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@ -295,9 +300,9 @@
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2012-03-21 Oleg Endo <olegendo@gcc.gnu.org>
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PR target/50751
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* gcc/target/sh/pr50751-1.c: New.
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* gcc/target/sh/pr50751-2.c: New.
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* gcc/target/sh/pr50751-3.c: New.
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* gcc.target/sh/pr50751-1.c: New.
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* gcc.target/sh/pr50751-2.c: New.
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* gcc.target/sh/pr50751-3.c: New.
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2012-03-21 Oleg Endo <olegendo@gcc.gnu.org>
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@ -1,7 +1,8 @@
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/* Testcase to check generation of a SH2A specific instruction PREF @Rm. */
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/* Testcase to check generation of a SH4 and SH2A operand cache prefetch
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instruction PREF @Rm. */
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/* { dg-do assemble {target sh*-*-*}} */
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/* { dg-options "-O0" } */
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/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" } */
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/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m2a*" "-m4*" } } */
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/* { dg-final { scan-assembler "pref"} } */
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void
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