From 6cb1b83e0fb35d45f33d155fa24a0dc2b4868a4b Mon Sep 17 00:00:00 2001 From: Bill Schmidt Date: Fri, 17 Apr 2015 14:50:50 +0000 Subject: [PATCH] re PR target/65787 (Miscompile due to bad vector swap optimization for little endian) [gcc] 2015-04-17 Bill Schmidt PR target/65787 * config/rs6000/rs6000.c (rtx_is_swappable_p): Handle case where vec_extract operation is wrapped in a PARALLEL with a CLOBBER. (adjust_extract): Likewise. [gcc/testsuite] 2015-04-17 Bill Schmidt PR target/65787 * gcc.target/powerpc/pr65787.c: New. From-SVN: r222182 --- gcc/ChangeLog | 7 +++++++ gcc/config/rs6000/rs6000.c | 16 +++++++++++++++- gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/gcc.target/powerpc/pr65787.c | 21 +++++++++++++++++++++ 4 files changed, 48 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/powerpc/pr65787.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index b7ebcf25e984..70addba21457 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2015-04-17 Bill Schmidt + + PR target/65787 + * config/rs6000/rs6000.c (rtx_is_swappable_p): Handle case where + vec_extract operation is wrapped in a PARALLEL with a CLOBBER. + (adjust_extract): Likewise. + 2015-04-17 Jakub Jelinek PR debug/65771 diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 4bb42213c873..3b31b122e193 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -34204,6 +34204,17 @@ rtx_is_swappable_p (rtx op, unsigned int *special) else return 0; + case PARALLEL: + /* A vec_extract operation may be wrapped in a PARALLEL with a + clobber, so account for that possibility. */ + if (XVECLEN (op, 0) != 2) + return 0; + + if (GET_CODE (XVECEXP (op, 0, 1)) != CLOBBER) + return 0; + + return rtx_is_swappable_p (XVECEXP (op, 0, 0), special); + case UNSPEC: { /* Various operations are unsafe for this optimization, at least @@ -34603,7 +34614,10 @@ permute_store (rtx_insn *insn) static void adjust_extract (rtx_insn *insn) { - rtx src = SET_SRC (PATTERN (insn)); + rtx pattern = PATTERN (insn); + if (GET_CODE (pattern) == PARALLEL) + pattern = XVECEXP (pattern, 0, 0); + rtx src = SET_SRC (pattern); /* The vec_select may be wrapped in a vec_duplicate for a splat, so account for that. */ rtx sel = GET_CODE (src) == VEC_DUPLICATE ? XEXP (src, 0) : src; diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index ea583b9f0b87..9a941df1bce3 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2015-04-17 Bill Schmidt + + PR target/65787 + * gcc.target/powerpc/pr65787.c: New. + 2015-04-17 Jakub Jelinek PR debug/65771 diff --git a/gcc/testsuite/gcc.target/powerpc/pr65787.c b/gcc/testsuite/gcc.target/powerpc/pr65787.c new file mode 100644 index 000000000000..c819be9a7073 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr65787.c @@ -0,0 +1,21 @@ +/* { dg-do compile { target { powerpc64le-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-options "-mcpu=power8 -O3" } */ +/* { dg-final { scan-assembler "xxsldwi \[0-9\]*,\[0-9\]*,\[0-9\]*,3" } } */ +/* { dg-final { scan-assembler-not "xxpermdi" } } */ + +/* This test verifies that a vector extract operand properly has its + lane changed by the swap optimization. Element 2 of LE corresponds + to element 1 of BE. When doublewords are swapped, this becomes + element 3 of BE, so we need to shift the vector left by 3 words + to be able to extract the correct value from BE element zero. */ + +typedef float v4f32 __attribute__ ((__vector_size__ (16))); + +void foo (float); +extern v4f32 x, y; + +int main() { + v4f32 z = x + y; + foo (z[2]); +}