mirror of git://gcc.gnu.org/git/gcc.git
frv-protos.h: Add a prototype to frv_legitimate_memory_operand and frv_const_unspec_p.
* config/frv/frv-protos.h: Add a prototype to frv_legitimate_memory_operand and frv_const_unspec_p. (frv_unspec): Move from frv.c. * config/frv/frv.c (frv_unspec): Move to frv-protos.h. (frv_const_unspec_p, frv_legitimate_memory_operand_): Export. (ldd_address_operand, fdpic_fptr_operand, frv_load_operand, gpr_or_fpr_operand, gpr_or_int12_operand, gpr_fpr_or_int12_operand, fpr_or_int6_operand, gpr_or_int10_operand, gpr_or_int_operand, int12_operand, int6_operand, int5_operand, uint5_operand, uint4_operand, uint1_operand, int_2word_operand, uint16_operand, upper_int16_operand, integer_register_operand, gpr_no_subreg_operand, fpr_operand, even_reg_operand, odd_reg_operand, even_gpr_operand, odd_gpr_operand, quad_fpr_operand, even_fpr_operand, odd_fpr_operand, dbl_memory_one_insn_operand, dbl_memory_two_insn_operand, move_destination_operand, movcc_fp_destination_operand, frv_function_symbol_referenced_p, move_source_operand, condexec_dest_operand, condexec_source_operand, reg_or_0_operand, lr_operand, fdpic_operand, got12_operand, const_unspec_operand, gpr_or_memory_operand, gpr_or_memory_operand_with_scratch, fpr_or_memory_operand, icc_operand, fcc_operand, cc_operand, icr_operand, fcr_operand, cr_operand, call_operand, sibcall_operand, symbolic_operand, relational_operator, integer_relational_operator, float_relational_operator, ccr_eqne_operator, minmax_operator, condexec_si_binary_operator, condexec_si_media_operator, condexec_si_divide_operator, condexec_si_unary_operator, condexec_sf_conv_operator, condexec_sf_add_operator, condexec_memory_operand, intop_compare_operator, acc_operand, even_acc_operand, quad_acc_operand, accg_operand: Move to predicates.md. * config/frv/frv.h (PREDICATE_CODES): Remove. * config/frv/frv.md: Include predicates.md. * config/frv/predicates.md: New. From-SVN: r97577
This commit is contained in:
Kazu Hirata
Kazu Hirata
parent
2f84c996da
commit
6d26dc3b6b
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@ -3,6 +3,43 @@
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* config/frv/frv.h (PREDICATE_CODES): Add CONST to
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gpr_or_int12_operand.
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* config/frv/frv-protos.h: Add a prototype to
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frv_legitimate_memory_operand and frv_const_unspec_p.
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(frv_unspec): Move from frv.c.
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* config/frv/frv.c (frv_unspec): Move to frv-protos.h.
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(frv_const_unspec_p, frv_legitimate_memory_operand_): Export.
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(ldd_address_operand, fdpic_fptr_operand, frv_load_operand,
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gpr_or_fpr_operand, gpr_or_int12_operand,
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gpr_fpr_or_int12_operand, fpr_or_int6_operand,
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gpr_or_int10_operand, gpr_or_int_operand, int12_operand,
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int6_operand, int5_operand, uint5_operand, uint4_operand,
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uint1_operand, int_2word_operand, uint16_operand,
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upper_int16_operand, integer_register_operand,
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gpr_no_subreg_operand, fpr_operand, even_reg_operand,
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odd_reg_operand, even_gpr_operand, odd_gpr_operand,
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quad_fpr_operand, even_fpr_operand, odd_fpr_operand,
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dbl_memory_one_insn_operand, dbl_memory_two_insn_operand,
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move_destination_operand, movcc_fp_destination_operand,
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frv_function_symbol_referenced_p, move_source_operand,
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condexec_dest_operand, condexec_source_operand,
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reg_or_0_operand, lr_operand, fdpic_operand, got12_operand,
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const_unspec_operand, gpr_or_memory_operand,
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gpr_or_memory_operand_with_scratch, fpr_or_memory_operand,
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icc_operand, fcc_operand, cc_operand, icr_operand,
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fcr_operand, cr_operand, call_operand, sibcall_operand,
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symbolic_operand, relational_operator,
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integer_relational_operator, float_relational_operator,
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ccr_eqne_operator, minmax_operator,
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condexec_si_binary_operator, condexec_si_media_operator,
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condexec_si_divide_operator, condexec_si_unary_operator,
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condexec_sf_conv_operator, condexec_sf_add_operator,
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condexec_memory_operand, intop_compare_operator, acc_operand,
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even_acc_operand, quad_acc_operand, accg_operand: Move to
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predicates.md.
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* config/frv/frv.h (PREDICATE_CODES): Remove.
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* config/frv/frv.md: Include predicates.md.
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* config/frv/predicates.md: New.
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2004-04-04 Richard Sandiford <rsandifo@redhat.com>
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PR target/19537
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@ -205,5 +205,18 @@ extern rtx frv_matching_accg_for_acc (rtx);
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extern void frv_expand_fdpic_call (rtx *, bool, bool);
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extern rtx frv_gen_GPsym2reg (rtx, rtx);
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extern void frv_output_dwarf_dtprel (FILE *, int, rtx);
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extern int frv_legitimate_memory_operand (rtx, enum machine_mode, int);
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/* Information about a relocation unspec. SYMBOL is the relocation symbol
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(a SYMBOL_REF or LABEL_REF), RELOC is the type of relocation and OFFSET
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is the constant addend. */
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struct frv_unspec {
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rtx symbol;
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int reloc;
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HOST_WIDE_INT offset;
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};
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extern bool frv_const_unspec_p (rtx, struct frv_unspec *);
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#endif
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1538
gcc/config/frv/frv.c
1538
gcc/config/frv/frv.c
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@ -2758,104 +2758,6 @@ do { \
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/* Miscellaneous Parameters. */
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/* Define this if you have defined special-purpose predicates in the file
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`MACHINE.c'. This macro is called within an initializer of an array of
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structures. The first field in the structure is the name of a predicate and
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the second field is an array of rtl codes. For each predicate, list all rtl
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codes that can be in expressions matched by the predicate. The list should
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have a trailing comma. Here is an example of two entries in the list for a
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typical RISC machine:
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#define PREDICATE_CODES \
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{"gen_reg_rtx_operand", {SUBREG, REG}}, \
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{"reg_or_short_cint_operand", {SUBREG, REG, CONST_INT}},
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Defining this macro does not affect the generated code (however, incorrect
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definitions that omit an rtl code that may be matched by the predicate can
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cause the compiler to malfunction). Instead, it allows the table built by
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`genrecog' to be more compact and efficient, thus speeding up the compiler.
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The most important predicates to include in the list specified by this macro
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are thoses used in the most insn patterns. */
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#define PREDICATE_CODES \
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{ "integer_register_operand", { REG, SUBREG }}, \
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{ "frv_load_operand", { REG, SUBREG, MEM }}, \
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{ "gpr_no_subreg_operand", { REG }}, \
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{ "gpr_or_fpr_operand", { REG, SUBREG }}, \
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{ "gpr_or_int12_operand", { REG, SUBREG, CONST_INT, CONST }}, \
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{ "gpr_fpr_or_int12_operand", { REG, SUBREG, CONST_INT }}, \
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{ "gpr_or_int10_operand", { REG, SUBREG, CONST_INT }}, \
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{ "gpr_or_int_operand", { REG, SUBREG, CONST_INT }}, \
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{ "move_source_operand", { REG, SUBREG, CONST_INT, MEM, \
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CONST_DOUBLE, CONST, \
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SYMBOL_REF, LABEL_REF }}, \
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{ "move_destination_operand", { REG, SUBREG, MEM }}, \
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{ "movcc_fp_destination_operand", { REG, SUBREG, MEM }}, \
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{ "condexec_source_operand", { REG, SUBREG, CONST_INT, MEM, \
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CONST_DOUBLE }}, \
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{ "condexec_dest_operand", { REG, SUBREG, MEM }}, \
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{ "reg_or_0_operand", { REG, SUBREG, CONST_INT }}, \
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{ "lr_operand", { REG }}, \
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{ "gpr_or_memory_operand", { REG, SUBREG, MEM }}, \
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{ "gpr_or_memory_operand_with_scratch", { REG, SUBREG, MEM }}, \
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{ "fpr_or_memory_operand", { REG, SUBREG, MEM }}, \
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{ "int12_operand", { CONST_INT }}, \
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{ "int_2word_operand", { CONST_INT, CONST_DOUBLE, \
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SYMBOL_REF, LABEL_REF, CONST }}, \
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{ "fdpic_operand", { REG }}, \
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{ "fdpic_fptr_operand", { REG }}, \
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{ "ldd_address_operand", { REG, SUBREG, PLUS }}, \
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{ "got12_operand", { CONST }}, \
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{ "const_unspec_operand", { CONST }}, \
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{ "icc_operand", { REG }}, \
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{ "fcc_operand", { REG }}, \
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{ "cc_operand", { REG }}, \
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{ "icr_operand", { REG }}, \
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{ "fcr_operand", { REG }}, \
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{ "cr_operand", { REG }}, \
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{ "fpr_operand", { REG, SUBREG }}, \
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{ "even_reg_operand", { REG, SUBREG }}, \
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{ "odd_reg_operand", { REG, SUBREG }}, \
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{ "even_gpr_operand", { REG, SUBREG }}, \
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{ "odd_gpr_operand", { REG, SUBREG }}, \
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{ "quad_fpr_operand", { REG, SUBREG }}, \
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{ "even_fpr_operand", { REG, SUBREG }}, \
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{ "odd_fpr_operand", { REG, SUBREG }}, \
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{ "dbl_memory_one_insn_operand", { MEM }}, \
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{ "dbl_memory_two_insn_operand", { MEM }}, \
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{ "call_operand", { REG, SUBREG, CONST_INT, \
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CONST, SYMBOL_REF }}, \
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{ "sibcall_operand", { REG, SUBREG, CONST_INT, \
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CONST }}, \
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{ "upper_int16_operand", { CONST_INT }}, \
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{ "uint16_operand", { CONST_INT }}, \
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{ "symbolic_operand", { SYMBOL_REF, CONST_INT }}, \
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{ "relational_operator", { EQ, NE, LE, LT, GE, GT, \
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LEU, LTU, GEU, GTU }}, \
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{ "integer_relational_operator", { EQ, NE, LE, LT, GE, GT, \
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LEU, LTU, GEU, GTU }}, \
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{ "float_relational_operator", { EQ, NE, LE, LT, GE, GT }}, \
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{ "ccr_eqne_operator", { EQ, NE }}, \
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{ "minmax_operator", { SMIN, SMAX, UMIN, UMAX }}, \
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{ "condexec_si_binary_operator", { PLUS, MINUS, AND, IOR, XOR, \
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ASHIFT, ASHIFTRT, LSHIFTRT }}, \
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{ "condexec_si_media_operator", { AND, IOR, XOR }}, \
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{ "condexec_si_divide_operator", { DIV, UDIV }}, \
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{ "condexec_si_unary_operator", { NOT, NEG }}, \
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{ "condexec_sf_add_operator", { PLUS, MINUS }}, \
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{ "condexec_sf_conv_operator", { ABS, NEG }}, \
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{ "intop_compare_operator", { PLUS, MINUS, AND, IOR, XOR, \
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ASHIFT, ASHIFTRT, LSHIFTRT }}, \
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{ "fpr_or_int6_operand", { REG, SUBREG, CONST_INT }}, \
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{ "int6_operand", { CONST_INT }}, \
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{ "int5_operand", { CONST_INT }}, \
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{ "uint5_operand", { CONST_INT }}, \
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{ "uint4_operand", { CONST_INT }}, \
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{ "uint1_operand", { CONST_INT }}, \
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{ "acc_operand", { REG, SUBREG }}, \
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{ "even_acc_operand", { REG, SUBREG }}, \
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{ "quad_acc_operand", { REG, SUBREG }}, \
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{ "accg_operand", { REG, SUBREG }},
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/* An alias for a machine mode name. This is the machine mode that elements of
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a jump-table should have. */
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#define CASE_VECTOR_MODE SImode
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@ -1504,6 +1504,7 @@
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;; )
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;;
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(include "predicates.md")
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;; ::::::::::::::::::::
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;; ::
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