mirror of git://gcc.gnu.org/git/gcc.git
mn10300: Clean up costing.
Address, register, memory and rtx costs bore little relation to reality. From-SVN: r168678
This commit is contained in:
Richard Henderson
Richard Henderson
parent
62d3f9b2ef
commit
72d6e3c594
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@ -1,5 +1,19 @@
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2011-01-11 Richard Henderson <rth@redhat.com>
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2011-01-11 Richard Henderson <rth@redhat.com>
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* config/mn10300/mn10300.c (mn10300_address_cost): Remove forward
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declaration. Rewrite for both speed and size.
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(mn10300_address_cost_1): Remove.
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(mn10300_register_move_cost): New.
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(mn10300_memory_move_cost): New.
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(mn10300_rtx_costs): Rewrite for both speed and size. Don't handle
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ZERO_EXTRACT. Do handle UNSPEC, arithmetic, logicals, compare,
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extensions, shifts, BSWAP, CLZ.
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(mn10300_wide_const_load_uses_clr): Remove.
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(TARGET_REGISTER_MOVE_COST): New.
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(TARGET_MEMORY_MOVE_COST): New.
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* config/mn10300/mn10300-protos.h: Update.
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* config/mn10300/mn10300.h (REGISTER_MOVE_COST): Remove.
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* config/mn10300/constraints.md ("R", "T"): Remove constraints.
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* config/mn10300/constraints.md ("R", "T"): Remove constraints.
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* config/mn10300/mn10300.c (mn10300_mask_ok_for_mem_btst): Remove.
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* config/mn10300/mn10300.c (mn10300_mask_ok_for_mem_btst): Remove.
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* config/mn10300/mn10300-protos.h: Update.
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* config/mn10300/mn10300-protos.h: Update.
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@ -39,7 +39,6 @@ extern Rclas mn10300_secondary_reload_class (Rclas, Mmode, rtx);
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extern Mmode mn10300_select_cc_mode (rtx);
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extern Mmode mn10300_select_cc_mode (rtx);
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extern int mn10300_store_multiple_operation (rtx, Mmode);
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extern int mn10300_store_multiple_operation (rtx, Mmode);
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extern int mn10300_symbolic_operand (rtx, Mmode);
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extern int mn10300_symbolic_operand (rtx, Mmode);
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extern bool mn10300_wide_const_load_uses_clr (rtx operands[2]);
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#endif /* RTX_CODE */
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#endif /* RTX_CODE */
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extern int mn10300_can_use_return_insn (void);
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extern int mn10300_can_use_return_insn (void);
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@ -75,8 +75,6 @@ enum processor_type mn10300_tune_cpu = PROCESSOR_DEFAULT;
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|| df_regs_ever_live_p (16) \
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|| df_regs_ever_live_p (16) \
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|| df_regs_ever_live_p (17)))
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|| df_regs_ever_live_p (17)))
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static int mn10300_address_cost (rtx, bool);
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/* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */
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/* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */
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static const struct default_options mn10300_option_optimization_table[] =
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static const struct default_options mn10300_option_optimization_table[] =
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{
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{
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@ -2034,180 +2032,340 @@ mn10300_legitimate_constant_p (rtx x)
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return true;
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return true;
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}
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}
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/* For addresses, costs are relative to "MOV (Rm),Rn". For AM33 this is
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the 3-byte fully general instruction; for MN103 this is the 2-byte form
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with an address register. */
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static int
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static int
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mn10300_address_cost_1 (rtx x, int *unsig)
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mn10300_address_cost (rtx x, bool speed)
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{
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{
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HOST_WIDE_INT i;
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rtx base, index;
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switch (GET_CODE (x))
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switch (GET_CODE (x))
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{
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{
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case REG:
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switch (REGNO_REG_CLASS (REGNO (x)))
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{
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case SP_REGS:
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*unsig = 1;
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return 0;
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case ADDRESS_REGS:
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return 1;
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case DATA_REGS:
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case EXTENDED_REGS:
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case FP_REGS:
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return 3;
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case NO_REGS:
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return 5;
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default:
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gcc_unreachable ();
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}
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case PLUS:
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case MINUS:
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case ASHIFT:
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case AND:
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case IOR:
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return (mn10300_address_cost_1 (XEXP (x, 0), unsig)
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+ mn10300_address_cost_1 (XEXP (x, 1), unsig));
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case EXPR_LIST:
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case SUBREG:
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case MEM:
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return mn10300_address_cost (XEXP (x, 0), !optimize_size);
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case ZERO_EXTEND:
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*unsig = 1;
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return mn10300_address_cost_1 (XEXP (x, 0), unsig);
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case CONST_INT:
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if (INTVAL (x) == 0)
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return 0;
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if (INTVAL (x) + (*unsig ? 0 : 0x80) < 0x100)
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return 1;
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if (INTVAL (x) + (*unsig ? 0 : 0x8000) < 0x10000)
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return 3;
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if (INTVAL (x) + (*unsig ? 0 : 0x800000) < 0x1000000)
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return 5;
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return 7;
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case CONST:
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case CONST:
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case SYMBOL_REF:
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case SYMBOL_REF:
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case LABEL_REF:
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case LABEL_REF:
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return 8;
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/* We assume all of these require a 32-bit constant, even though
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some symbol and label references can be relaxed. */
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return speed ? 1 : 4;
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case REG:
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case SUBREG:
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case POST_INC:
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return 0;
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case POST_MODIFY:
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/* Assume any symbolic offset is a 32-bit constant. */
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i = (CONST_INT_P (XEXP (x, 1)) ? INTVAL (XEXP (x, 1)) : 0x12345678);
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if (IN_RANGE (i, -128, 127))
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return speed ? 0 : 1;
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if (speed)
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return 1;
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if (IN_RANGE (i, -0x800000, 0x7fffff))
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return 3;
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return 4;
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case PLUS:
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base = XEXP (x, 0);
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index = XEXP (x, 1);
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if (register_operand (index, SImode))
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{
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/* Attempt to minimize the number of registers in the address.
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This is similar to what other ports do. */
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if (register_operand (base, SImode))
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return 1;
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base = XEXP (x, 1);
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index = XEXP (x, 0);
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}
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/* Assume any symbolic offset is a 32-bit constant. */
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i = (CONST_INT_P (XEXP (x, 1)) ? INTVAL (XEXP (x, 1)) : 0x12345678);
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if (IN_RANGE (i, -128, 127))
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return speed ? 0 : 1;
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if (IN_RANGE (i, -32768, 32767))
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return speed ? 0 : 2;
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return speed ? 2 : 6;
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default:
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default:
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gcc_unreachable ();
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return rtx_cost (x, MEM, speed);
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}
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}
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}
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}
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/* Implement the TARGET_REGISTER_MOVE_COST hook.
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Recall that the base value of 2 is required by assumptions elsewhere
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in the body of the compiler, and that cost 2 is special-cased as an
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early exit from reload meaning no work is required. */
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static int
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static int
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mn10300_address_cost (rtx x, bool speed ATTRIBUTE_UNUSED)
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mn10300_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
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reg_class_t ifrom, reg_class_t ito)
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{
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{
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int s = 0;
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enum reg_class from = (enum reg_class) ifrom;
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return mn10300_address_cost_1 (x, &s);
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enum reg_class to = (enum reg_class) ito;
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enum reg_class scratch, test;
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/* Simplify the following code by unifying the fp register classes. */
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if (to == FP_ACC_REGS)
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to = FP_REGS;
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if (from == FP_ACC_REGS)
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from = FP_REGS;
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/* Diagnose invalid moves by costing them as two moves. */
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scratch = NO_REGS;
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test = from;
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if (to == SP_REGS)
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scratch = (TARGET_AM33 ? GENERAL_REGS : ADDRESS_REGS);
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else if (to == FP_REGS && to != from)
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scratch = GENERAL_REGS;
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else
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{
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test = to;
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if (from == SP_REGS)
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scratch = (TARGET_AM33 ? GENERAL_REGS : ADDRESS_REGS);
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else if (from == FP_REGS && to != from)
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scratch = GENERAL_REGS;
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}
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if (scratch != NO_REGS && !reg_class_subset_p (test, scratch))
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return (mn10300_register_move_cost (VOIDmode, from, scratch)
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+ mn10300_register_move_cost (VOIDmode, scratch, to));
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/* From here on, all we need consider are legal combinations. */
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if (optimize_size)
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{
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/* The scale here is bytes * 2. */
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if (from == to && (to == ADDRESS_REGS || to == DATA_REGS))
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return 2;
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if (from == SP_REGS)
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return (to == ADDRESS_REGS ? 2 : 6);
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/* For MN103, all remaining legal moves are two bytes. */
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if (TARGET_AM33)
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return 4;
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if (to == SP_REGS)
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return (from == ADDRESS_REGS ? 4 : 6);
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if ((from == ADDRESS_REGS || from == DATA_REGS)
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&& (to == ADDRESS_REGS || to == DATA_REGS))
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return 4;
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if (to == EXTENDED_REGS)
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return (to == from ? 6 : 4);
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/* What's left are SP_REGS, FP_REGS, or combinations of the above. */
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return 6;
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}
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else
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{
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/* The scale here is cycles * 2. */
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if (to == FP_REGS)
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return 8;
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if (from == FP_REGS)
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return 4;
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/* All legal moves between integral registers are single cycle. */
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return 2;
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}
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}
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}
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static bool
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/* Implement the TARGET_MEMORY_MOVE_COST hook.
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mn10300_rtx_costs (rtx x, int code, int outer_code, int *total,
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bool speed ATTRIBUTE_UNUSED)
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Given lack of the form of the address, this must be speed-relative,
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though we should never be less expensive than a size-relative register
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move cost above. This is not a problem. */
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static int
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mn10300_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
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reg_class_t iclass, bool in ATTRIBUTE_UNUSED)
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{
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{
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enum reg_class rclass = (enum reg_class) iclass;
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if (rclass == FP_REGS)
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return 8;
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return 6;
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}
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/* Implement the TARGET_RTX_COSTS hook.
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Speed-relative costs are relative to COSTS_N_INSNS, which is intended
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to represent cycles. Size-relative costs are in bytes. */
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static bool
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mn10300_rtx_costs (rtx x, int code, int outer_code, int *ptotal, bool speed)
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{
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/* This value is used for SYMBOL_REF etc where we want to pretend
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we have a full 32-bit constant. */
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HOST_WIDE_INT i = 0x12345678;
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int total;
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switch (code)
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switch (code)
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{
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{
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case CONST_INT:
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case CONST_INT:
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/* Zeros are extremely cheap. */
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i = INTVAL (x);
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if (INTVAL (x) == 0 && (outer_code == SET || outer_code == COMPARE))
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do_int_costs:
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*total = 0;
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if (speed)
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/* If it fits in 8 bits, then it's still relatively cheap. */
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{
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else if (INT_8_BITS (INTVAL (x)))
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if (outer_code == SET)
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*total = 1;
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{
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/* This is the "base" cost, includes constants where either the
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/* 16-bit integer loads have latency 1, 32-bit loads 2. */
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upper or lower 16bits are all zeros. */
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if (IN_RANGE (i, -32768, 32767))
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else if (INT_16_BITS (INTVAL (x))
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total = COSTS_N_INSNS (1);
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|| (INTVAL (x) & 0xffff) == 0
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|| (INTVAL (x) & 0xffff0000) == 0)
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*total = 2;
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else
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else
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*total = 4;
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total = COSTS_N_INSNS (2);
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return true;
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}
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else
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{
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/* 16-bit integer operands don't affect latency;
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24-bit and 32-bit operands add a cycle. */
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if (IN_RANGE (i, -32768, 32767))
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total = 0;
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else
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total = COSTS_N_INSNS (1);
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}
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}
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else
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{
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if (outer_code == SET)
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{
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if (i == 0)
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total = 1;
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else if (IN_RANGE (i, -128, 127))
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total = 2;
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else if (IN_RANGE (i, -32768, 32767))
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total = 3;
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else
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total = 6;
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}
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else
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{
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/* Reference here is ADD An,Dn, vs ADD imm,Dn. */
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if (IN_RANGE (i, -128, 127))
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total = 0;
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else if (IN_RANGE (i, -32768, 32767))
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total = 2;
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else if (TARGET_AM33 && IN_RANGE (i, -0x01000000, 0x00ffffff))
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total = 3;
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else
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total = 4;
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}
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}
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goto alldone;
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case CONST:
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case CONST:
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case LABEL_REF:
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case LABEL_REF:
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case SYMBOL_REF:
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case SYMBOL_REF:
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/* These are more costly than a CONST_INT, but we can relax them,
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so they're less costly than a CONST_DOUBLE. */
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*total = 6;
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return true;
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case CONST_DOUBLE:
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case CONST_DOUBLE:
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/* We don't optimize CONST_DOUBLEs well nor do we relax them well,
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/* We assume all of these require a 32-bit constant, even though
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so their cost is very high. */
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some symbol and label references can be relaxed. */
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*total = 8;
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goto do_int_costs;
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return true;
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case ZERO_EXTRACT:
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case UNSPEC:
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/* This is cheap, we can use btst. */
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switch (XINT (x, 1))
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if (outer_code == COMPARE)
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{
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*total = 0;
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case UNSPEC_PIC:
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return false;
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case UNSPEC_GOT:
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case UNSPEC_GOTOFF:
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case UNSPEC_PLT:
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case UNSPEC_GOTSYM_OFF:
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/* The PIC unspecs also resolve to a 32-bit constant. */
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goto do_int_costs;
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default:
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/* Assume any non-listed unspec is some sort of arithmetic. */
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goto do_arith_costs;
|
||||||
|
}
|
||||||
|
|
||||||
|
case PLUS:
|
||||||
|
/* Notice the size difference of INC and INC4. */
|
||||||
|
if (!speed && outer_code == SET && CONST_INT_P (XEXP (x, 1)))
|
||||||
|
{
|
||||||
|
i = INTVAL (XEXP (x, 1));
|
||||||
|
if (i == 1 || i == 4)
|
||||||
|
{
|
||||||
|
total = 1 + rtx_cost (XEXP (x, 0), PLUS, speed);
|
||||||
|
goto alldone;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
goto do_arith_costs;
|
||||||
|
|
||||||
|
case MINUS:
|
||||||
|
case AND:
|
||||||
|
case IOR:
|
||||||
|
case XOR:
|
||||||
|
case NOT:
|
||||||
|
case NEG:
|
||||||
|
case ZERO_EXTEND:
|
||||||
|
case SIGN_EXTEND:
|
||||||
|
case COMPARE:
|
||||||
|
case BSWAP:
|
||||||
|
case CLZ:
|
||||||
|
do_arith_costs:
|
||||||
|
total = (speed ? COSTS_N_INSNS (1) : 2);
|
||||||
|
break;
|
||||||
|
|
||||||
|
case ASHIFT:
|
||||||
|
/* Notice the size difference of ASL2 and variants. */
|
||||||
|
if (!speed && CONST_INT_P (XEXP (x, 1)))
|
||||||
|
switch (INTVAL (XEXP (x, 1)))
|
||||||
|
{
|
||||||
|
case 1:
|
||||||
|
case 2:
|
||||||
|
total = 1;
|
||||||
|
goto alldone;
|
||||||
|
case 3:
|
||||||
|
case 4:
|
||||||
|
total = 2;
|
||||||
|
goto alldone;
|
||||||
|
}
|
||||||
|
/* FALLTHRU */
|
||||||
|
|
||||||
|
case ASHIFTRT:
|
||||||
|
case LSHIFTRT:
|
||||||
|
total = (speed ? COSTS_N_INSNS (1) : 3);
|
||||||
|
goto alldone;
|
||||||
|
|
||||||
/* ??? This probably needs more work. */
|
|
||||||
case MOD:
|
|
||||||
case DIV:
|
|
||||||
case MULT:
|
case MULT:
|
||||||
*total = 8;
|
total = (speed ? COSTS_N_INSNS (3) : 2);
|
||||||
|
break;
|
||||||
|
|
||||||
|
case DIV:
|
||||||
|
case UDIV:
|
||||||
|
case MOD:
|
||||||
|
case UMOD:
|
||||||
|
total = (speed ? COSTS_N_INSNS (39)
|
||||||
|
/* Include space to load+retrieve MDR. */
|
||||||
|
: code == MOD || code == UMOD ? 6 : 4);
|
||||||
|
break;
|
||||||
|
|
||||||
|
case MEM:
|
||||||
|
total = mn10300_address_cost (XEXP (x, 0), speed);
|
||||||
|
if (speed)
|
||||||
|
total = COSTS_N_INSNS (2 + total);
|
||||||
|
goto alldone;
|
||||||
|
|
||||||
|
default:
|
||||||
|
/* Probably not implemented. Assume external call. */
|
||||||
|
total = (speed ? COSTS_N_INSNS (10) : 7);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
*ptotal = total;
|
||||||
|
return false;
|
||||||
|
|
||||||
|
alldone:
|
||||||
|
*ptotal = total;
|
||||||
return true;
|
return true;
|
||||||
|
|
||||||
default:
|
|
||||||
return false;
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Check whether a constant used to initialize a DImode or DFmode can
|
|
||||||
use a clr instruction. The code here must be kept in sync with
|
|
||||||
movdf and movdi. */
|
|
||||||
|
|
||||||
bool
|
|
||||||
mn10300_wide_const_load_uses_clr (rtx operands[2])
|
|
||||||
{
|
|
||||||
long val[2] = {0, 0};
|
|
||||||
|
|
||||||
if ((! REG_P (operands[0]))
|
|
||||||
|| REGNO_REG_CLASS (REGNO (operands[0])) != DATA_REGS)
|
|
||||||
return false;
|
|
||||||
|
|
||||||
switch (GET_CODE (operands[1]))
|
|
||||||
{
|
|
||||||
case CONST_INT:
|
|
||||||
{
|
|
||||||
rtx low, high;
|
|
||||||
split_double (operands[1], &low, &high);
|
|
||||||
val[0] = INTVAL (low);
|
|
||||||
val[1] = INTVAL (high);
|
|
||||||
}
|
|
||||||
break;
|
|
||||||
|
|
||||||
case CONST_DOUBLE:
|
|
||||||
if (GET_MODE (operands[1]) == DFmode)
|
|
||||||
{
|
|
||||||
REAL_VALUE_TYPE rv;
|
|
||||||
|
|
||||||
REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
|
|
||||||
REAL_VALUE_TO_TARGET_DOUBLE (rv, val);
|
|
||||||
}
|
|
||||||
else if (GET_MODE (operands[1]) == VOIDmode
|
|
||||||
|| GET_MODE (operands[1]) == DImode)
|
|
||||||
{
|
|
||||||
val[0] = CONST_DOUBLE_LOW (operands[1]);
|
|
||||||
val[1] = CONST_DOUBLE_HIGH (operands[1]);
|
|
||||||
}
|
|
||||||
break;
|
|
||||||
|
|
||||||
default:
|
|
||||||
return false;
|
|
||||||
}
|
|
||||||
|
|
||||||
return val[0] == 0 || val[1] == 0;
|
|
||||||
}
|
|
||||||
/* If using PIC, mark a SYMBOL_REF for a non-global symbol so that we
|
/* If using PIC, mark a SYMBOL_REF for a non-global symbol so that we
|
||||||
may access it using GOTOFF instead of GOT. */
|
may access it using GOTOFF instead of GOT. */
|
||||||
|
|
||||||
|
|
@ -2502,10 +2660,14 @@ mn10300_conditional_register_usage (void)
|
||||||
#undef TARGET_LEGITIMIZE_ADDRESS
|
#undef TARGET_LEGITIMIZE_ADDRESS
|
||||||
#define TARGET_LEGITIMIZE_ADDRESS mn10300_legitimize_address
|
#define TARGET_LEGITIMIZE_ADDRESS mn10300_legitimize_address
|
||||||
|
|
||||||
#undef TARGET_RTX_COSTS
|
|
||||||
#define TARGET_RTX_COSTS mn10300_rtx_costs
|
|
||||||
#undef TARGET_ADDRESS_COST
|
#undef TARGET_ADDRESS_COST
|
||||||
#define TARGET_ADDRESS_COST mn10300_address_cost
|
#define TARGET_ADDRESS_COST mn10300_address_cost
|
||||||
|
#undef TARGET_REGISTER_MOVE_COST
|
||||||
|
#define TARGET_REGISTER_MOVE_COST mn10300_register_move_cost
|
||||||
|
#undef TARGET_MEMORY_MOVE_COST
|
||||||
|
#define TARGET_MEMORY_MOVE_COST mn10300_memory_move_cost
|
||||||
|
#undef TARGET_RTX_COSTS
|
||||||
|
#define TARGET_RTX_COSTS mn10300_rtx_costs
|
||||||
|
|
||||||
#undef TARGET_ASM_FILE_START
|
#undef TARGET_ASM_FILE_START
|
||||||
#define TARGET_ASM_FILE_START mn10300_file_start
|
#define TARGET_ASM_FILE_START mn10300_file_start
|
||||||
|
|
|
||||||
|
|
@ -600,19 +600,6 @@ struct cum_arg
|
||||||
#define SELECT_CC_MODE(OP, X, Y) mn10300_select_cc_mode (X)
|
#define SELECT_CC_MODE(OP, X, Y) mn10300_select_cc_mode (X)
|
||||||
#define REVERSIBLE_CC_MODE(MODE) 0
|
#define REVERSIBLE_CC_MODE(MODE) 0
|
||||||
|
|
||||||
#define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
|
|
||||||
((CLASS1 == CLASS2 && (CLASS1 == ADDRESS_REGS || CLASS1 == DATA_REGS)) ? 2 :\
|
|
||||||
((CLASS1 == ADDRESS_REGS || CLASS1 == DATA_REGS) && \
|
|
||||||
(CLASS2 == ADDRESS_REGS || CLASS2 == DATA_REGS)) ? 4 : \
|
|
||||||
(CLASS1 == SP_REGS && CLASS2 == ADDRESS_REGS) ? 2 : \
|
|
||||||
(CLASS1 == ADDRESS_REGS && CLASS2 == SP_REGS) ? 4 : \
|
|
||||||
! TARGET_AM33 ? 6 : \
|
|
||||||
(CLASS1 == SP_REGS || CLASS2 == SP_REGS) ? 6 : \
|
|
||||||
(CLASS1 == CLASS2 && CLASS1 == EXTENDED_REGS) ? 6 : \
|
|
||||||
(CLASS1 == FP_REGS || CLASS2 == FP_REGS) ? 6 : \
|
|
||||||
(CLASS1 == EXTENDED_REGS || CLASS2 == EXTENDED_REGS) ? 4 : \
|
|
||||||
4)
|
|
||||||
|
|
||||||
/* Nonzero if access to memory by bytes or half words is no faster
|
/* Nonzero if access to memory by bytes or half words is no faster
|
||||||
than accessing full words. */
|
than accessing full words. */
|
||||||
#define SLOW_BYTE_ACCESS 1
|
#define SLOW_BYTE_ACCESS 1
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue