git
/
gcc
mirror of git://gcc.gnu.org/git/gcc.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Fix 16-bit floating point ordering. 

2025-10-17  Michael Meissner  <meissner@linux.ibm.com>

gcc/

	* config/rs6000/ffloat16.md (vec_unpacks_hi_v8hf): Fix ordering issue.
	(vec_unpacks_lo_v8hf): Likewise.
	(vec_unpacks_hi_v8bf): Likewise.
	(vec_unpacks_lo_v8bf): Likewise.
This commit is contained in:
Michael Meissner 2025-10-17 03:49:39 -04:00
parent 357d0be634
commit 7b0c41ca37
1 changed files with 4 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
gcc/config/rs6000/float16.md
View File

@ -1013,7 +1013,7 @@
{ {
rtx reg = gen_reg_rtx (V8HFmode); rtx reg = gen_reg_rtx (V8HFmode);
rs6000_expand_interleave (reg, operands[1], operands[1], BYTES_BIG_ENDIAN); rs6000_expand_interleave (reg, operands[1], operands[1], !BYTES_BIG_ENDIAN);
emit_insn (gen_xvcvhpsp_v8hf (operands[0], reg)); emit_insn (gen_xvcvhpsp_v8hf (operands[0], reg));
DONE; DONE;
}) })
@ -1025,7 +1025,7 @@
{ {
rtx reg = gen_reg_rtx (V8HFmode); rtx reg = gen_reg_rtx (V8HFmode);
rs6000_expand_interleave (reg, operands[1], operands[1], !BYTES_BIG_ENDIAN); rs6000_expand_interleave (reg, operands[1], operands[1], BYTES_BIG_ENDIAN);
emit_insn (gen_xvcvhpsp_v8hf (operands[0], reg)); emit_insn (gen_xvcvhpsp_v8hf (operands[0], reg));
DONE; DONE;
}) })
@ -1047,7 +1047,7 @@
{ {
rtx reg = gen_reg_rtx (V8BFmode); rtx reg = gen_reg_rtx (V8BFmode);
rs6000_expand_interleave (reg, operands[1], operands[1], BYTES_BIG_ENDIAN); rs6000_expand_interleave (reg, operands[1], operands[1], !BYTES_BIG_ENDIAN);
emit_insn (gen_xvcvbf16spn_v8bf (operands[0], reg)); emit_insn (gen_xvcvbf16spn_v8bf (operands[0], reg));
DONE; DONE;
}) })
@ -1059,7 +1059,7 @@
{ {
rtx reg = gen_reg_rtx (V8BFmode); rtx reg = gen_reg_rtx (V8BFmode);
rs6000_expand_interleave (reg, operands[1], operands[1], !BYTES_BIG_ENDIAN); rs6000_expand_interleave (reg, operands[1], operands[1], BYTES_BIG_ENDIAN);
emit_insn (gen_xvcvbf16spn_v8bf (operands[0], reg)); emit_insn (gen_xvcvbf16spn_v8bf (operands[0], reg));
DONE; DONE;
}) })