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mips.h (ISA_HAS_FP4): Remove TARGET_FLOAT64 restriction for ISA_MIPS32R2. 

* config/mips/mips.h (ISA_HAS_FP4): Remove TARGET_FLOAT64
	restriction for ISA_MIPS32R2.
	(ISA_HAS_LXC1_SXC1): New macro.
	(ISA_HAS_FP_MADD4_MSUB4): Remove ISA_MIPS32R2 special-casing.
	(ISA_HAS_NMADD4_NMSUB4): Likewise.
	(ISA_HAS_FP_RECIP_RSQRT): Likewise.
	(ISA_HAS_PREFETCHX): Redefine in terms of ISA_HAS_FP4.
	* config/mips/mips.md (*<ANYF:loadx>_<P:mode>): Use
	ISA_HAS_LXC1_SXC1 rather than ISA_HAS_FP4.
	(*<ANYF:storex>_<P:mode>): Likewise.

From-SVN: r205130
This commit is contained in:
Maciej W. Rozycki 2013-11-20 17:18:12 +00:00 committed by Maciej W. Rozycki
parent 287c5d3812
commit 7cfe3cc182
3 changed files with 26 additions and 14 deletions
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13
gcc/ChangeLog
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@ -1,3 +1,16 @@
2013-11-20 Maciej W. Rozycki <macro@codesourcery.com>
* config/mips/mips.h (ISA_HAS_FP4): Remove TARGET_FLOAT64
restriction for ISA_MIPS32R2.
(ISA_HAS_LXC1_SXC1): New macro.
(ISA_HAS_FP_MADD4_MSUB4): Remove ISA_MIPS32R2 special-casing.
(ISA_HAS_NMADD4_NMSUB4): Likewise.
(ISA_HAS_FP_RECIP_RSQRT): Likewise.
(ISA_HAS_PREFETCHX): Redefine in terms of ISA_HAS_FP4.
* config/mips/mips.md (*<ANYF:loadx>_<P:mode>): Use
ISA_HAS_LXC1_SXC1 rather than ISA_HAS_FP4.
(*<ANYF:storex>_<P:mode>): Likewise.
2013-11-20 Maciej W. Rozycki <macro@codesourcery.com> 2013-11-20 Maciej W. Rozycki <macro@codesourcery.com>
* config/mips/mips.h (ISA_HAS_FP_RECIP_RSQRT): New macro. * config/mips/mips.h (ISA_HAS_FP_RECIP_RSQRT): New macro.

23
gcc/config/mips/mips.h
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@ -882,13 +882,18 @@ struct mips_cpu_info {
/* This is a catch all for other mips4 instructions: indexed load, the /* This is a catch all for other mips4 instructions: indexed load, the
FP madd and msub instructions, and the FP recip and recip sqrt FP madd and msub instructions, and the FP recip and recip sqrt
instructions. */ instructions. Note that this macro should only be used by other
ISA_HAS_* macros. */
#define ISA_HAS_FP4 ((ISA_MIPS4 \ #define ISA_HAS_FP4 ((ISA_MIPS4 \
|| (ISA_MIPS32R2 && TARGET_FLOAT64) \ || ISA_MIPS32R2 \
|| ISA_MIPS64 \ || ISA_MIPS64 \
|| ISA_MIPS64R2) \ || ISA_MIPS64R2) \
&& !TARGET_MIPS16) && !TARGET_MIPS16)
/* ISA has floating-point indexed load and store instructions
(LWXC1, LDXC1, SWXC1 and SDXC1). */
#define ISA_HAS_LXC1_SXC1 ISA_HAS_FP4
/* ISA has paired-single instructions. */ /* ISA has paired-single instructions. */
#define ISA_HAS_PAIRED_SINGLE (ISA_MIPS32R2 || ISA_MIPS64 || ISA_MIPS64R2) #define ISA_HAS_PAIRED_SINGLE (ISA_MIPS32R2 || ISA_MIPS64 || ISA_MIPS64R2)
@ -906,16 +911,14 @@ struct mips_cpu_info {
#define GENERATE_MADD_MSUB (TARGET_IMADD && !TARGET_MIPS16) #define GENERATE_MADD_MSUB (TARGET_IMADD && !TARGET_MIPS16)
/* ISA has floating-point madd and msub instructions 'd = a * b [+-] c'. */ /* ISA has floating-point madd and msub instructions 'd = a * b [+-] c'. */
#define ISA_HAS_FP_MADD4_MSUB4 (ISA_HAS_FP4 \ #define ISA_HAS_FP_MADD4_MSUB4 ISA_HAS_FP4
|| (ISA_MIPS32R2 && !TARGET_MIPS16))
/* ISA has floating-point madd and msub instructions 'c = a * b [+-] c'. */ /* ISA has floating-point madd and msub instructions 'c = a * b [+-] c'. */
#define ISA_HAS_FP_MADD3_MSUB3 TARGET_LOONGSON_2EF #define ISA_HAS_FP_MADD3_MSUB3 TARGET_LOONGSON_2EF
/* ISA has floating-point nmadd and nmsub instructions /* ISA has floating-point nmadd and nmsub instructions
'd = -((a * b) [+-] c)'. */ 'd = -((a * b) [+-] c)'. */
#define ISA_HAS_NMADD4_NMSUB4 (ISA_HAS_FP4 \ #define ISA_HAS_NMADD4_NMSUB4 ISA_HAS_FP4
|| (ISA_MIPS32R2 && !TARGET_MIPS16))
/* ISA has floating-point nmadd and nmsub instructions /* ISA has floating-point nmadd and nmsub instructions
'c = -((a * b) [+-] c)'. */ 'c = -((a * b) [+-] c)'. */
@ -926,7 +929,7 @@ struct mips_cpu_info {
doubles are stored in pairs of FPRs, so for safety's sake, we apply doubles are stored in pairs of FPRs, so for safety's sake, we apply
this restriction to the MIPS IV ISA too. */ this restriction to the MIPS IV ISA too. */
#define ISA_HAS_FP_RECIP_RSQRT(MODE) \ #define ISA_HAS_FP_RECIP_RSQRT(MODE) \
((((ISA_HAS_FP4 || ISA_MIPS32R2) \ (((ISA_HAS_FP4 \
&& ((MODE) == SFmode \ && ((MODE) == SFmode \
|| ((TARGET_FLOAT64 \ || ((TARGET_FLOAT64 \
|| ISA_MIPS32R2 \ || ISA_MIPS32R2 \
@ -1006,11 +1009,7 @@ struct mips_cpu_info {
'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT. 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
(prefx is a cop1x instruction, so can only be used if FP is (prefx is a cop1x instruction, so can only be used if FP is
enabled.) */ enabled.) */
#define ISA_HAS_PREFETCHX ((ISA_MIPS4 \ #define ISA_HAS_PREFETCHX ISA_HAS_FP4
|| ISA_MIPS32R2 \
|| ISA_MIPS64 \
|| ISA_MIPS64R2) \
&& !TARGET_MIPS16)
/* True if trunc.w.s and trunc.w.d are real (not synthetic) /* True if trunc.w.s and trunc.w.d are real (not synthetic)
instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d

4
gcc/config/mips/mips.md
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@ -4440,7 +4440,7 @@
[(set (match_operand:ANYF 0 "register_operand" "=f") [(set (match_operand:ANYF 0 "register_operand" "=f")
(mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d") (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d")
(match_operand:P 2 "register_operand" "d"))))] (match_operand:P 2 "register_operand" "d"))))]
"ISA_HAS_FP4" "ISA_HAS_LXC1_SXC1"
"<ANYF:loadx>\t%0,%1(%2)" "<ANYF:loadx>\t%0,%1(%2)"
[(set_attr "type" "fpidxload") [(set_attr "type" "fpidxload")
(set_attr "mode" "<ANYF:UNITMODE>")]) (set_attr "mode" "<ANYF:UNITMODE>")])
@ -4449,7 +4449,7 @@
[(set (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d") [(set (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d")
(match_operand:P 2 "register_operand" "d"))) (match_operand:P 2 "register_operand" "d")))
(match_operand:ANYF 0 "register_operand" "f"))] (match_operand:ANYF 0 "register_operand" "f"))]
"ISA_HAS_FP4" "ISA_HAS_LXC1_SXC1"
"<ANYF:storex>\t%0,%1(%2)" "<ANYF:storex>\t%0,%1(%2)"
[(set_attr "type" "fpidxstore") [(set_attr "type" "fpidxstore")
(set_attr "mode" "<ANYF:UNITMODE>")]) (set_attr "mode" "<ANYF:UNITMODE>")])