mirror of git://gcc.gnu.org/git/gcc.git
backport: re PR target/69228 (Default mask is not allowed for AVX512 prefetch gather/scatter insns)
Backport from mainline 2016-01-13 Alexander Fomin <alexander.fomin@intel.com> gcc/ PR target/69228 * config/i386/sse.md (define_expand "avx512pf_gatherpf<mode>sf"): Change first operand predicate from register_or_constm1_operand to register_operand. (define_expand "avx512pf_gatherpf<mode>df"): Likewise. (define_expand "avx512pf_scatterpf<mode>sf"): Likewise. (define_expand "avx512pf_scatterpf<mode>df"): Likewise. (define_insn "*avx512pf_gatherpf<mode>sf"): Remove. (define_insn "*avx512pf_gatherpf<mode>df"): Likewise. (define_insn "*avx512pf_scatterpf<mode>sf"): Likewise. (define_insn "*avx512pf_scatterpf<mode>df"): Likewise. * config/i386/i386.c (ix86_expand_builtin): Remove first operand comparison with constm1_rtx from vec_prefetch_gen part. gcc/testsuite PR target/69228 * gcc.target/i386/avx512pf-vscatterpf0dpd-1.c: Adjust. * gcc.target/i386/avx512pf-vscatterpf0dps-1.c: Likewise. * gcc.target/i386/avx512pf-vscatterpf0qpd-1.c: Likewise. * gcc.target/i386/avx512pf-vscatterpf0qps-1.c: Likewise. * gcc.target/i386/avx512pf-vscatterpf1dpd-1.c: Likewise. * gcc.target/i386/avx512pf-vscatterpf1dps-1.c: Likewise. * gcc.target/i386/avx512pf-vscatterpf1qpd-1.c: Likewise. * gcc.target/i386/avx512pf-vscatterpf1qps-1.c: Likewise. From-SVN: r232412
This commit is contained in:
Alexander Fomin
Alexander Fomin
parent
c57ac69f3a
commit
83d875c4b4
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@ -1,3 +1,22 @@
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2016-01-15 Alexander Fomin <alexander.fomin@intel.com>
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Backport from mainline
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2016-01-13 Alexander Fomin <alexander.fomin@intel.com>
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PR target/69228
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* config/i386/sse.md (define_expand "avx512pf_gatherpf<mode>sf"):
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Change first operand predicate from register_or_constm1_operand
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to register_operand.
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(define_expand "avx512pf_gatherpf<mode>df"): Likewise.
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(define_expand "avx512pf_scatterpf<mode>sf"): Likewise.
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(define_expand "avx512pf_scatterpf<mode>df"): Likewise.
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(define_insn "*avx512pf_gatherpf<mode>sf"): Remove.
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(define_insn "*avx512pf_gatherpf<mode>df"): Likewise.
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(define_insn "*avx512pf_scatterpf<mode>sf"): Likewise.
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(define_insn "*avx512pf_scatterpf<mode>df"): Likewise.
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* config/i386/i386.c (ix86_expand_builtin): Remove first operand
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comparison with constm1_rtx from vec_prefetch_gen part.
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2016-01-13 Richard Biener <rguenther@suse.de>
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PR tree-optimization/69013
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@ -40259,13 +40259,12 @@ rdseed_step:
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op0 = fixup_modeless_constant (op0, mode0);
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if (GET_MODE (op0) == mode0
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|| (GET_MODE (op0) == VOIDmode && op0 != constm1_rtx))
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if (GET_MODE (op0) == mode0 || GET_MODE (op0) == VOIDmode)
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{
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if (!insn_data[icode].operand[0].predicate (op0, mode0))
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op0 = copy_to_mode_reg (mode0, op0);
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}
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else if (op0 != constm1_rtx)
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else
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{
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op0 = copy_to_reg (op0);
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op0 = simplify_gen_subreg (mode0, op0, GET_MODE (op0), 0);
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@ -15210,7 +15210,7 @@
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(define_expand "avx512pf_gatherpf<mode>sf"
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[(unspec
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[(match_operand:<avx512fmaskmode> 0 "register_or_constm1_operand")
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[(match_operand:<avx512fmaskmode> 0 "register_operand")
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(mem:<GATHER_SCATTER_SF_MEM_MODE>
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(match_par_dup 5
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[(match_operand 2 "vsib_address_operand")
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@ -15252,37 +15252,10 @@
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(set_attr "prefix" "evex")
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(set_attr "mode" "XI")])
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(define_insn "*avx512pf_gatherpf<mode>sf"
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[(unspec
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[(const_int -1)
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(match_operator:<GATHER_SCATTER_SF_MEM_MODE> 4 "vsib_mem_operator"
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[(unspec:P
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[(match_operand:P 1 "vsib_address_operand" "Tv")
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(match_operand:VI48_512 0 "register_operand" "v")
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(match_operand:SI 2 "const1248_operand" "n")]
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UNSPEC_VSIBADDR)])
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(match_operand:SI 3 "const_2_to_3_operand" "n")]
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UNSPEC_GATHER_PREFETCH)]
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"TARGET_AVX512PF"
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{
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switch (INTVAL (operands[3]))
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{
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case 3:
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return "vgatherpf0<ssemodesuffix>ps\t{%4|%4}";
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case 2:
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return "vgatherpf1<ssemodesuffix>ps\t{%4|%4}";
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default:
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gcc_unreachable ();
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}
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}
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[(set_attr "type" "sse")
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(set_attr "prefix" "evex")
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(set_attr "mode" "XI")])
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;; Packed double variants
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(define_expand "avx512pf_gatherpf<mode>df"
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[(unspec
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[(match_operand:<avx512fmaskmode> 0 "register_or_constm1_operand")
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[(match_operand:<avx512fmaskmode> 0 "register_operand")
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(mem:V8DF
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(match_par_dup 5
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[(match_operand 2 "vsib_address_operand")
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@ -15324,37 +15297,10 @@
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(set_attr "prefix" "evex")
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(set_attr "mode" "XI")])
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(define_insn "*avx512pf_gatherpf<mode>df"
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[(unspec
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[(const_int -1)
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(match_operator:V8DF 4 "vsib_mem_operator"
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[(unspec:P
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[(match_operand:P 1 "vsib_address_operand" "Tv")
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(match_operand:VI4_256_8_512 0 "register_operand" "v")
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(match_operand:SI 2 "const1248_operand" "n")]
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UNSPEC_VSIBADDR)])
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(match_operand:SI 3 "const_2_to_3_operand" "n")]
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UNSPEC_GATHER_PREFETCH)]
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"TARGET_AVX512PF"
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{
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switch (INTVAL (operands[3]))
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{
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case 3:
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return "vgatherpf0<ssemodesuffix>pd\t{%4|%4}";
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case 2:
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return "vgatherpf1<ssemodesuffix>pd\t{%4|%4}";
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default:
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gcc_unreachable ();
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}
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}
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[(set_attr "type" "sse")
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(set_attr "prefix" "evex")
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(set_attr "mode" "XI")])
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;; Packed float variants
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(define_expand "avx512pf_scatterpf<mode>sf"
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[(unspec
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[(match_operand:<avx512fmaskmode> 0 "register_or_constm1_operand")
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[(match_operand:<avx512fmaskmode> 0 "register_operand")
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(mem:<GATHER_SCATTER_SF_MEM_MODE>
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(match_par_dup 5
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[(match_operand 2 "vsib_address_operand")
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@ -15398,39 +15344,10 @@
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(set_attr "prefix" "evex")
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(set_attr "mode" "XI")])
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(define_insn "*avx512pf_scatterpf<mode>sf"
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[(unspec
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[(const_int -1)
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(match_operator:<GATHER_SCATTER_SF_MEM_MODE> 4 "vsib_mem_operator"
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[(unspec:P
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[(match_operand:P 1 "vsib_address_operand" "Tv")
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(match_operand:VI48_512 0 "register_operand" "v")
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(match_operand:SI 2 "const1248_operand" "n")]
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UNSPEC_VSIBADDR)])
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(match_operand:SI 3 "const2367_operand" "n")]
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UNSPEC_SCATTER_PREFETCH)]
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"TARGET_AVX512PF"
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{
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switch (INTVAL (operands[3]))
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{
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case 3:
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case 7:
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return "vscatterpf0<ssemodesuffix>ps\t{%4|%4}";
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case 2:
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case 6:
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return "vscatterpf1<ssemodesuffix>ps\t{%4|%4}";
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default:
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gcc_unreachable ();
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}
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}
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[(set_attr "type" "sse")
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(set_attr "prefix" "evex")
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(set_attr "mode" "XI")])
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;; Packed double variants
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(define_expand "avx512pf_scatterpf<mode>df"
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[(unspec
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[(match_operand:<avx512fmaskmode> 0 "register_or_constm1_operand")
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[(match_operand:<avx512fmaskmode> 0 "register_operand")
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(mem:V8DF
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(match_par_dup 5
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[(match_operand 2 "vsib_address_operand")
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@ -15474,35 +15391,6 @@
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(set_attr "prefix" "evex")
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(set_attr "mode" "XI")])
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(define_insn "*avx512pf_scatterpf<mode>df"
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[(unspec
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[(const_int -1)
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(match_operator:V8DF 4 "vsib_mem_operator"
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[(unspec:P
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[(match_operand:P 1 "vsib_address_operand" "Tv")
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(match_operand:VI4_256_8_512 0 "register_operand" "v")
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(match_operand:SI 2 "const1248_operand" "n")]
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UNSPEC_VSIBADDR)])
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(match_operand:SI 3 "const2367_operand" "n")]
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UNSPEC_SCATTER_PREFETCH)]
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"TARGET_AVX512PF"
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{
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switch (INTVAL (operands[3]))
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{
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case 3:
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case 7:
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return "vscatterpf0<ssemodesuffix>pd\t{%4|%4}";
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case 2:
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case 6:
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return "vscatterpf1<ssemodesuffix>pd\t{%4|%4}";
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default:
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gcc_unreachable ();
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}
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}
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[(set_attr "type" "sse")
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(set_attr "prefix" "evex")
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(set_attr "mode" "XI")])
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(define_insn "avx512er_exp2<mode><mask_name><round_saeonly_name>"
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[(set (match_operand:VF_512 0 "register_operand" "=v")
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(unspec:VF_512
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@ -1,3 +1,18 @@
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2016-01-15 Alexander Fomin <alexander.fomin@intel.com>
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Backport from mainline
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2016-01-13 Alexander Fomin <alexander.fomin@intel.com>
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PR target/69228
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* gcc.target/i386/avx512pf-vscatterpf0dpd-1.c: Adjust.
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* gcc.target/i386/avx512pf-vscatterpf0dps-1.c: Likewise.
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* gcc.target/i386/avx512pf-vscatterpf0qpd-1.c: Likewise.
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* gcc.target/i386/avx512pf-vscatterpf0qps-1.c: Likewise.
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* gcc.target/i386/avx512pf-vscatterpf1dpd-1.c: Likewise.
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* gcc.target/i386/avx512pf-vscatterpf1dps-1.c: Likewise.
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* gcc.target/i386/avx512pf-vscatterpf1qpd-1.c: Likewise.
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* gcc.target/i386/avx512pf-vscatterpf1qps-1.c: Likewise.
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2016-01-12 James Greenhalgh <james.greenhalgh@arm.com>
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Backport from mainline r222186.
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@ -1,7 +1,6 @@
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/* { dg-do compile } */
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/* { dg-options "-mavx512pf -O2" } */
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/* { dg-final { scan-assembler-times "vscatterpf0dpd\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\]*\\)(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vscatterpf0dpd\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\]*\\)\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vscatterpf0dpd\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\]*\\)\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 2 } } */
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#include <immintrin.h>
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volatile __m256i idx;
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/* { dg-do compile } */
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/* { dg-options "-mavx512pf -O2" } */
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/* { dg-final { scan-assembler-times "vscatterpf0dps\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\]*\\)(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vscatterpf0dps\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\]*\\)\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vscatterpf0dps\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\]*\\)\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 2 } } */
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#include <immintrin.h>
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/* { dg-do compile } */
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/* { dg-options "-mavx512pf -O2" } */
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/* { dg-final { scan-assembler-times "vscatterpf0qpd\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\]*\\)(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vscatterpf0qpd\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\]*\\)\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vscatterpf0qpd\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\]*\\)\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 2 } } */
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#include <immintrin.h>
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/* { dg-do compile } */
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/* { dg-options "-mavx512pf -O2" } */
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/* { dg-final { scan-assembler-times "vscatterpf0qps\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\]*\\)(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vscatterpf0qps\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\]*\\)\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vscatterpf0qps\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\]*\\)\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 2 } } */
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#include <immintrin.h>
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/* { dg-do compile } */
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/* { dg-options "-mavx512pf -O2" } */
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/* { dg-final { scan-assembler-times "vscatterpf1dpd\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\]*\\)(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vscatterpf1dpd\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\]*\\)\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vscatterpf1dpd\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\]*\\)\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 2 } } */
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#include <immintrin.h>
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/* { dg-do compile } */
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/* { dg-options "-mavx512pf -O2" } */
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/* { dg-final { scan-assembler-times "vscatterpf1dps\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\]*\\)(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vscatterpf1dps\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\]*\\)\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vscatterpf1dps\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\]*\\)\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 2 } } */
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#include <immintrin.h>
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/* { dg-do compile } */
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/* { dg-options "-mavx512pf -O2" } */
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/* { dg-final { scan-assembler-times "vscatterpf1qpd\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\]*\\)(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vscatterpf1qpd\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\]*\\)\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vscatterpf1qpd\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\]*\\)\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 2 } } */
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#include <immintrin.h>
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/* { dg-do compile } */
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/* { dg-options "-mavx512pf -O2" } */
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/* { dg-final { scan-assembler-times "vscatterpf1qps\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\]*\\)(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vscatterpf1qps\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\]*\\)\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vscatterpf1qps\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\]*\\)\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 2 } } */
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#include <immintrin.h>
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