mirror of git://gcc.gnu.org/git/gcc.git
sparc-modes.def (CCV): New.
* config/sparc/sparc-modes.def (CCV): New.
(CCXV): Likewise.
* config/sparc/predicates.md (v_comparison_operator): New.
(icc_comparison_operator): Add support for CCV/CCXV.
(xcc_comparison_operator): Likewise.
* config/sparc/sparc.c (output_cbranch): Likewise.
(sparc_print_operand): Likewise.
* config/sparc/sparc.md (UNSPEC_{ADD,SUB,NEG}V): New constants.
(uaddvdi4): New expander.
(addvdi4): Likewise.
(uaddvdi4_sp32): New instruction.
(addvdi4_sp32): Likewise.
(uaddvsi4): New expander.
(addvsi4): Likewise.
(cmp_ccc_plus_sltu_set): New instruction.
(cmp_ccv_plus): Likewise.
(cmp_ccxv_plus): Likewise.
(cmp_ccv_plus_set): Likewise.
(cmp_ccxv_plus_set): Likewise.
(cmp_ccv_plus_sltu_set): Likewise.
(uaddvdi4): New expander.
(subvdi4): Likewise.
(usubdi4_sp32): New instruction.
(subvdi4_sp32): Likewise.
(usubvsi4): New expander.
(subvsi4): Likewise.
(cmpsi_minus_sltu_set): New instruction.
(cmp_ccv_minus): Likewise.
(cmp_ccxv_minus): Likewise.
(cmp_ccv_minus_set): Likewise.
(cmp_ccxv_minus_set): Likewise.
(cmp_ccv_minus_sltu_set): Likewise.
(unegvdi3): New expander.
(negvdi3): Likewise.
(unegdi3_sp32): New instruction.
(negvdi3_sp32): Likewise.
(unegvsi3): New expander.
(negvsi3): Likewise.
(cmp_ccc_neg_sltu_set): New instruction.
(cmp_ccv_neg): Likewise.
(cmp_ccxv_neg): Likewise.
(cmp_ccv_neg_set): Likewise.
(cmp_ccxv_neg_set): Likewise.
(cmp_ccv_neg_sltu_set): Likewise.
From-SVN: r241397
This commit is contained in:
Eric Botcazou
Eric Botcazou
parent
d17f2c3b49
commit
8572922996
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@ -1,3 +1,50 @@
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2016-10-21 Eric Botcazou <ebotcazou@adacore.com>
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* config/sparc/sparc-modes.def (CCV): New.
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(CCXV): Likewise.
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* config/sparc/predicates.md (v_comparison_operator): New.
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(icc_comparison_operator): Add support for CCV/CCXV.
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(xcc_comparison_operator): Likewise.
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* config/sparc/sparc.c (output_cbranch): Likewise.
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(sparc_print_operand): Likewise.
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* config/sparc/sparc.md (UNSPEC_{ADD,SUB,NEG}V): New constants.
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(uaddvdi4): New expander.
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(addvdi4): Likewise.
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(uaddvdi4_sp32): New instruction.
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(addvdi4_sp32): Likewise.
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(uaddvsi4): New expander.
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(addvsi4): Likewise.
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(cmp_ccc_plus_sltu_set): New instruction.
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(cmp_ccv_plus): Likewise.
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(cmp_ccxv_plus): Likewise.
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(cmp_ccv_plus_set): Likewise.
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(cmp_ccxv_plus_set): Likewise.
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(cmp_ccv_plus_sltu_set): Likewise.
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(uaddvdi4): New expander.
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(subvdi4): Likewise.
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(usubdi4_sp32): New instruction.
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(subvdi4_sp32): Likewise.
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(usubvsi4): New expander.
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(subvsi4): Likewise.
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(cmpsi_minus_sltu_set): New instruction.
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(cmp_ccv_minus): Likewise.
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(cmp_ccxv_minus): Likewise.
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(cmp_ccv_minus_set): Likewise.
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(cmp_ccxv_minus_set): Likewise.
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(cmp_ccv_minus_sltu_set): Likewise.
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(unegvdi3): New expander.
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(negvdi3): Likewise.
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(unegdi3_sp32): New instruction.
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(negvdi3_sp32): Likewise.
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(unegvsi3): New expander.
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(negvsi3): Likewise.
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(cmp_ccc_neg_sltu_set): New instruction.
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(cmp_ccv_neg): Likewise.
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(cmp_ccxv_neg): Likewise.
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(cmp_ccv_neg_set): Likewise.
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(cmp_ccxv_neg_set): Likewise.
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(cmp_ccv_neg_sltu_set): Likewise.
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2016-10-21 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
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2016-10-21 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
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PR rtl-optimization/78038
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PR rtl-optimization/78038
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@ -420,6 +420,10 @@
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(define_predicate "c_comparison_operator"
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(define_predicate "c_comparison_operator"
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(match_code "ltu,geu"))
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(match_code "ltu,geu"))
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;; Return true if OP is a valid comparison operator for CCVmode.
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(define_predicate "v_comparison_operator"
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(match_code "eq,ne"))
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;; Return true if OP is an integer comparison operator. This allows
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;; Return true if OP is an integer comparison operator. This allows
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;; the use of MATCH_OPERATOR to recognize all the branch insns.
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;; the use of MATCH_OPERATOR to recognize all the branch insns.
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(define_predicate "icc_comparison_operator"
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(define_predicate "icc_comparison_operator"
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@ -436,6 +440,9 @@
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case CCCmode:
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case CCCmode:
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case CCXCmode:
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case CCXCmode:
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return c_comparison_operator (op, mode);
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return c_comparison_operator (op, mode);
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case CCVmode:
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case CCXVmode:
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return v_comparison_operator (op, mode);
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default:
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default:
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return false;
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return false;
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}
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}
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@ -34,6 +34,10 @@ FLOAT_MODE (TF, 16, ieee_quad_format);
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they explicitly set the C flag (unsigned overflow). Only the unsigned
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they explicitly set the C flag (unsigned overflow). Only the unsigned
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<,>= operators can be used in conjunction with it.
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<,>= operators can be used in conjunction with it.
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We also have a CCVmode which is used by the arithmetic instructions when
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they explicitly set the V flag (signed overflow). Only the =,!= operators
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can be used in conjunction with it.
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We also have two modes to indicate that the relevant condition code is
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We also have two modes to indicate that the relevant condition code is
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in the floating-point condition code register. One for comparisons which
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in the floating-point condition code register. One for comparisons which
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will generate an exception if the result is unordered (CCFPEmode) and
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will generate an exception if the result is unordered (CCFPEmode) and
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@ -46,6 +50,8 @@ CC_MODE (CCNZ);
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CC_MODE (CCXNZ);
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CC_MODE (CCXNZ);
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CC_MODE (CCC);
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CC_MODE (CCC);
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CC_MODE (CCXC);
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CC_MODE (CCXC);
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CC_MODE (CCV);
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CC_MODE (CCXV);
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CC_MODE (CCFP);
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CC_MODE (CCFP);
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CC_MODE (CCFPE);
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CC_MODE (CCFPE);
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@ -2784,8 +2784,9 @@ select_cc_mode (enum rtx_code op, rtx x, rtx y)
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gcc_unreachable ();
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gcc_unreachable ();
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}
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}
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}
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}
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else if (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
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else if ((GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
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|| GET_CODE (x) == NEG || GET_CODE (x) == ASHIFT)
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|| GET_CODE (x) == NEG || GET_CODE (x) == ASHIFT)
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&& y == const0_rtx)
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{
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{
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if (TARGET_ARCH64 && GET_MODE (x) == DImode)
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if (TARGET_ARCH64 && GET_MODE (x) == DImode)
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return CCXNZmode;
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return CCXNZmode;
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@ -2803,6 +2804,18 @@ select_cc_mode (enum rtx_code op, rtx x, rtx y)
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return CCCmode;
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return CCCmode;
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}
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}
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/* This is for the [u]addvdi4_sp32 and [u]subvdi4_sp32 patterns. */
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if (!TARGET_ARCH64 && GET_MODE (x) == DImode)
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{
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if (GET_CODE (y) == UNSPEC
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&& (XINT (y, 1) == UNSPEC_ADDV
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|| XINT (y, 1) == UNSPEC_SUBV
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|| XINT (y, 1) == UNSPEC_NEGV))
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return CCVmode;
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else
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return CCCmode;
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}
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if (TARGET_ARCH64 && GET_MODE (x) == DImode)
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if (TARGET_ARCH64 && GET_MODE (x) == DImode)
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return CCXmode;
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return CCXmode;
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else
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else
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@ -7724,9 +7737,15 @@ output_cbranch (rtx op, rtx dest, int label, int reversed, int annul,
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switch (code)
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switch (code)
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{
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{
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case NE:
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case NE:
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if (mode == CCVmode || mode == CCXVmode)
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branch = "bvs";
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else
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branch = "bne";
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branch = "bne";
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break;
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break;
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case EQ:
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case EQ:
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if (mode == CCVmode || mode == CCXVmode)
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branch = "bvc";
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else
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branch = "be";
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branch = "be";
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break;
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break;
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case GE:
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case GE:
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@ -7794,6 +7813,7 @@ output_cbranch (rtx op, rtx dest, int label, int reversed, int annul,
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case CCmode:
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case CCmode:
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case CCNZmode:
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case CCNZmode:
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case CCCmode:
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case CCCmode:
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case CCVmode:
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labelno = "%%icc, ";
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labelno = "%%icc, ";
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if (v8)
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if (v8)
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labelno = "";
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labelno = "";
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@ -7801,6 +7821,7 @@ output_cbranch (rtx op, rtx dest, int label, int reversed, int annul,
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case CCXmode:
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case CCXmode:
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case CCXNZmode:
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case CCXNZmode:
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case CCXCmode:
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case CCXCmode:
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case CCXVmode:
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labelno = "%%xcc, ";
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labelno = "%%xcc, ";
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gcc_assert (!v8);
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gcc_assert (!v8);
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break;
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break;
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@ -8804,11 +8825,13 @@ sparc_print_operand (FILE *file, rtx x, int code)
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case CCmode:
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case CCmode:
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case CCNZmode:
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case CCNZmode:
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case CCCmode:
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case CCCmode:
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case CCVmode:
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s = "%icc";
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s = "%icc";
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break;
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break;
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case CCXmode:
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case CCXmode:
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case CCXNZmode:
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case CCXNZmode:
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case CCXCmode:
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case CCXCmode:
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case CCXVmode:
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s = "%xcc";
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s = "%xcc";
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break;
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break;
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default:
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default:
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@ -8883,9 +8906,15 @@ sparc_print_operand (FILE *file, rtx x, int code)
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switch (GET_CODE (x))
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switch (GET_CODE (x))
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{
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{
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case NE:
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case NE:
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if (mode == CCVmode || mode == CCXVmode)
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s = "vs";
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else
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s = "ne";
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s = "ne";
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break;
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break;
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case EQ:
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case EQ:
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if (mode == CCVmode || mode == CCXVmode)
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s = "vc";
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else
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s = "e";
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s = "e";
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break;
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break;
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case GE:
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case GE:
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@ -92,6 +92,10 @@
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UNSPEC_MUL8
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UNSPEC_MUL8
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UNSPEC_MUL8SU
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UNSPEC_MUL8SU
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UNSPEC_MULDSU
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UNSPEC_MULDSU
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UNSPEC_ADDV
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UNSPEC_SUBV
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UNSPEC_NEGV
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])
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])
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(define_c_enum "unspecv" [
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(define_c_enum "unspecv" [
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@ -3714,6 +3718,51 @@
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}
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}
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})
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})
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(define_expand "uaddvdi4"
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[(parallel [(set (reg:CCXC CC_REG)
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(compare:CCXC (plus:DI (match_operand:DI 1 "register_operand")
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(match_operand:DI 2 "arith_add_operand"))
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(match_dup 1)))
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(set (match_operand:DI 0 "register_operand")
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(plus:DI (match_dup 1) (match_dup 2)))])
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(set (pc) (if_then_else (ltu (reg:CCXC CC_REG) (const_int 0))
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(label_ref (match_operand 3))
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(pc)))]
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""
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{
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if (!TARGET_64BIT)
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{
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emit_insn (gen_uaddvdi4_sp32 (operands[0], operands[1], operands[2]));
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rtx x = gen_rtx_LTU (VOIDmode, gen_rtx_REG (CCCmode, SPARC_ICC_REG),
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const0_rtx);
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emit_jump_insn (gen_cbranchcc4 (x, XEXP (x, 0), XEXP (x, 1), operands[3]));
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DONE;
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}
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})
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(define_expand "addvdi4"
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[(parallel [(set (reg:CCXV CC_REG)
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(compare:CCXV (plus:DI (match_operand:DI 1 "register_operand")
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|
(match_operand:DI 2 "arith_add_operand"))
|
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|
(unspec:DI [(match_dup 1) (match_dup 2)]
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|
UNSPEC_ADDV)))
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|
(set (match_operand:DI 0 "register_operand")
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|
(plus:DI (match_dup 1) (match_dup 2)))])
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|
(set (pc) (if_then_else (ne (reg:CCXV CC_REG) (const_int 0))
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|
(label_ref (match_operand 3))
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|
(pc)))]
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|
""
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|
{
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|
if (!TARGET_64BIT)
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{
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|
emit_insn (gen_addvdi4_sp32 (operands[0], operands[1], operands[2]));
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rtx x = gen_rtx_NE (VOIDmode, gen_rtx_REG (CCVmode, SPARC_ICC_REG),
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const0_rtx);
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emit_jump_insn (gen_cbranchcc4 (x, XEXP (x, 0), XEXP (x, 1), operands[3]));
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|
DONE;
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|
}
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|
})
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|
|
||||||
(define_insn_and_split "adddi3_sp32"
|
(define_insn_and_split "adddi3_sp32"
|
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[(set (match_operand:DI 0 "register_operand" "=&r")
|
[(set (match_operand:DI 0 "register_operand" "=&r")
|
||||||
(plus:DI (match_operand:DI 1 "register_operand" "%r")
|
(plus:DI (match_operand:DI 1 "register_operand" "%r")
|
||||||
|
|
@ -3740,6 +3789,80 @@
|
||||||
}
|
}
|
||||||
[(set_attr "length" "2")])
|
[(set_attr "length" "2")])
|
||||||
|
|
||||||
|
(define_insn_and_split "uaddvdi4_sp32"
|
||||||
|
[(set (reg:CCC CC_REG)
|
||||||
|
(compare:CCC (plus:DI (match_operand:DI 1 "register_operand" "%r")
|
||||||
|
(match_operand:DI 2 "arith_double_operand" "rHI"))
|
||||||
|
(match_dup 1)))
|
||||||
|
(set (match_operand:DI 0 "register_operand" "=&r")
|
||||||
|
(plus:DI (match_dup 1) (match_dup 2)))]
|
||||||
|
"!TARGET_ARCH64"
|
||||||
|
"#"
|
||||||
|
"&& reload_completed"
|
||||||
|
[(parallel [(set (reg:CCC CC_REG)
|
||||||
|
(compare:CCC (plus:SI (match_dup 4) (match_dup 5))
|
||||||
|
(match_dup 4)))
|
||||||
|
(set (match_dup 3)
|
||||||
|
(plus:SI (match_dup 4) (match_dup 5)))])
|
||||||
|
(parallel [(set (reg:CCC CC_REG)
|
||||||
|
(compare:CCC (zero_extend:DI
|
||||||
|
(plus:SI (plus:SI (match_dup 7) (match_dup 8))
|
||||||
|
(ltu:SI (reg:CCC CC_REG)
|
||||||
|
(const_int 0))))
|
||||||
|
(plus:DI (plus:DI (zero_extend:DI (match_dup 7))
|
||||||
|
(zero_extend:DI (match_dup 8)))
|
||||||
|
(ltu:DI (reg:CCC CC_REG)
|
||||||
|
(const_int 0)))))
|
||||||
|
(set (match_dup 6)
|
||||||
|
(plus:SI (plus:SI (match_dup 7) (match_dup 8))
|
||||||
|
(ltu:SI (reg:CCC CC_REG)
|
||||||
|
(const_int 0))))])]
|
||||||
|
{
|
||||||
|
operands[3] = gen_lowpart (SImode, operands[0]);
|
||||||
|
operands[4] = gen_lowpart (SImode, operands[1]);
|
||||||
|
operands[5] = gen_lowpart (SImode, operands[2]);
|
||||||
|
operands[6] = gen_highpart (SImode, operands[0]);
|
||||||
|
operands[7] = gen_highpart_mode (SImode, DImode, operands[1]);
|
||||||
|
operands[8] = gen_highpart_mode (SImode, DImode, operands[2]);
|
||||||
|
}
|
||||||
|
[(set_attr "length" "2")])
|
||||||
|
|
||||||
|
(define_insn_and_split "addvdi4_sp32"
|
||||||
|
[(set (reg:CCV CC_REG)
|
||||||
|
(compare:CCV (plus:DI (match_operand:DI 1 "register_operand" "%r")
|
||||||
|
(match_operand:DI 2 "arith_double_operand" "rHI"))
|
||||||
|
(unspec:DI [(match_dup 1) (match_dup 2)] UNSPEC_ADDV)))
|
||||||
|
(set (match_operand:DI 0 "register_operand" "=&r")
|
||||||
|
(plus:DI (match_dup 1) (match_dup 2)))]
|
||||||
|
"!TARGET_ARCH64"
|
||||||
|
"#"
|
||||||
|
"&& reload_completed"
|
||||||
|
[(parallel [(set (reg:CCC CC_REG)
|
||||||
|
(compare:CCC (plus:SI (match_dup 4) (match_dup 5))
|
||||||
|
(match_dup 4)))
|
||||||
|
(set (match_dup 3)
|
||||||
|
(plus:SI (match_dup 4) (match_dup 5)))])
|
||||||
|
(parallel [(set (reg:CCV CC_REG)
|
||||||
|
(compare:CCV (plus:SI (plus:SI (match_dup 7) (match_dup 8))
|
||||||
|
(ltu:SI (reg:CCC CC_REG)
|
||||||
|
(const_int 0)))
|
||||||
|
(unspec:SI [(plus:SI (match_dup 7) (match_dup 8))
|
||||||
|
(ltu:SI (reg:CCC CC_REG)
|
||||||
|
(const_int 0))]
|
||||||
|
UNSPEC_ADDV)))
|
||||||
|
(set (match_dup 6)
|
||||||
|
(plus:SI (plus:SI (match_dup 7) (match_dup 8))
|
||||||
|
(ltu:SI (reg:CCC CC_REG) (const_int 0))))])]
|
||||||
|
{
|
||||||
|
operands[3] = gen_lowpart (SImode, operands[0]);
|
||||||
|
operands[4] = gen_lowpart (SImode, operands[1]);
|
||||||
|
operands[5] = gen_lowpart (SImode, operands[2]);
|
||||||
|
operands[6] = gen_highpart (SImode, operands[0]);
|
||||||
|
operands[7] = gen_highpart_mode (SImode, DImode, operands[1]);
|
||||||
|
operands[8] = gen_highpart_mode (SImode, DImode, operands[2]);
|
||||||
|
}
|
||||||
|
[(set_attr "length" "2")])
|
||||||
|
|
||||||
(define_insn_and_split "*addx_extend_sp32"
|
(define_insn_and_split "*addx_extend_sp32"
|
||||||
[(set (match_operand:DI 0 "register_operand" "=r")
|
[(set (match_operand:DI 0 "register_operand" "=r")
|
||||||
(zero_extend:DI (plus:SI (plus:SI
|
(zero_extend:DI (plus:SI (plus:SI
|
||||||
|
|
@ -3797,6 +3920,31 @@
|
||||||
[(set_attr "type" "*,*")
|
[(set_attr "type" "*,*")
|
||||||
(set_attr "fptype" "*,*")])
|
(set_attr "fptype" "*,*")])
|
||||||
|
|
||||||
|
(define_expand "uaddvsi4"
|
||||||
|
[(parallel [(set (reg:CCC CC_REG)
|
||||||
|
(compare:CCC (plus:SI (match_operand:SI 1 "register_operand")
|
||||||
|
(match_operand:SI 2 "arith_operand"))
|
||||||
|
(match_dup 1)))
|
||||||
|
(set (match_operand:SI 0 "register_operand")
|
||||||
|
(plus:SI (match_dup 1) (match_dup 2)))])
|
||||||
|
(set (pc) (if_then_else (ltu (reg:CCC CC_REG) (const_int 0))
|
||||||
|
(label_ref (match_operand 3))
|
||||||
|
(pc)))]
|
||||||
|
"")
|
||||||
|
|
||||||
|
(define_expand "addvsi4"
|
||||||
|
[(parallel [(set (reg:CCV CC_REG)
|
||||||
|
(compare:CCV (plus:SI (match_operand:SI 1 "register_operand")
|
||||||
|
(match_operand:SI 2 "arith_operand"))
|
||||||
|
(unspec:SI [(match_dup 1) (match_dup 2)]
|
||||||
|
UNSPEC_ADDV)))
|
||||||
|
(set (match_operand:SI 0 "register_operand")
|
||||||
|
(plus:SI (match_dup 1) (match_dup 2)))])
|
||||||
|
(set (pc) (if_then_else (ne (reg:CCV CC_REG) (const_int 0))
|
||||||
|
(label_ref (match_operand 3))
|
||||||
|
(pc)))]
|
||||||
|
"")
|
||||||
|
|
||||||
(define_insn "*cmp_ccnz_plus"
|
(define_insn "*cmp_ccnz_plus"
|
||||||
[(set (reg:CCNZ CC_REG)
|
[(set (reg:CCNZ CC_REG)
|
||||||
(compare:CCNZ (plus:SI (match_operand:SI 0 "register_operand" "%r")
|
(compare:CCNZ (plus:SI (match_operand:SI 0 "register_operand" "%r")
|
||||||
|
|
@ -3877,6 +4025,79 @@
|
||||||
"addcc\t%1, %2, %0"
|
"addcc\t%1, %2, %0"
|
||||||
[(set_attr "type" "compare")])
|
[(set_attr "type" "compare")])
|
||||||
|
|
||||||
|
(define_insn "*cmp_ccc_plus_sltu_set"
|
||||||
|
[(set (reg:CCC CC_REG)
|
||||||
|
(compare:CCC (zero_extend:DI
|
||||||
|
(plus:SI
|
||||||
|
(plus:SI (match_operand:SI 1 "register_operand" "%r")
|
||||||
|
(match_operand:SI 2 "arith_operand" "rI"))
|
||||||
|
(ltu:SI (reg:CCC CC_REG) (const_int 0))))
|
||||||
|
(plus:DI (plus:DI (zero_extend:DI (match_dup 1))
|
||||||
|
(zero_extend:DI (match_dup 2)))
|
||||||
|
(ltu:DI (reg:CCC CC_REG) (const_int 0)))))
|
||||||
|
(set (match_operand:SI 0 "register_operand" "=r")
|
||||||
|
(plus:SI (plus:SI (match_dup 1) (match_dup 2))
|
||||||
|
(ltu:SI (reg:CCC CC_REG) (const_int 0))))]
|
||||||
|
""
|
||||||
|
"addxcc\t%1, %2, %0"
|
||||||
|
[(set_attr "type" "compare")])
|
||||||
|
|
||||||
|
(define_insn "*cmp_ccv_plus"
|
||||||
|
[(set (reg:CCV CC_REG)
|
||||||
|
(compare:CCV (plus:SI (match_operand:SI 0 "register_operand" "%r")
|
||||||
|
(match_operand:SI 1 "arith_operand" "rI"))
|
||||||
|
(unspec:SI [(match_dup 0) (match_dup 1)] UNSPEC_ADDV)))]
|
||||||
|
""
|
||||||
|
"addcc\t%0, %1, %%g0"
|
||||||
|
[(set_attr "type" "compare")])
|
||||||
|
|
||||||
|
(define_insn "*cmp_ccxv_plus"
|
||||||
|
[(set (reg:CCXV CC_REG)
|
||||||
|
(compare:CCXV (plus:DI (match_operand:DI 0 "register_operand" "%r")
|
||||||
|
(match_operand:DI 1 "arith_operand" "rI"))
|
||||||
|
(unspec:DI [(match_dup 0) (match_dup 1)] UNSPEC_ADDV)))]
|
||||||
|
"TARGET_ARCH64"
|
||||||
|
"addcc\t%0, %1, %%g0"
|
||||||
|
[(set_attr "type" "compare")])
|
||||||
|
|
||||||
|
(define_insn "*cmp_ccv_plus_set"
|
||||||
|
[(set (reg:CCV CC_REG)
|
||||||
|
(compare:CCV (plus:SI (match_operand:SI 1 "register_operand" "%r")
|
||||||
|
(match_operand:SI 2 "arith_operand" "rI"))
|
||||||
|
(unspec:SI [(match_dup 1) (match_dup 2)] UNSPEC_ADDV)))
|
||||||
|
(set (match_operand:SI 0 "register_operand" "=r")
|
||||||
|
(plus:SI (match_dup 1) (match_dup 2)))]
|
||||||
|
""
|
||||||
|
"addcc\t%1, %2, %0"
|
||||||
|
[(set_attr "type" "compare")])
|
||||||
|
|
||||||
|
(define_insn "*cmp_ccxv_plus_set"
|
||||||
|
[(set (reg:CCXV CC_REG)
|
||||||
|
(compare:CCXV (plus:DI (match_operand:DI 1 "register_operand" "%r")
|
||||||
|
(match_operand:DI 2 "arith_operand" "rI"))
|
||||||
|
(unspec:DI [(match_dup 1) (match_dup 2)] UNSPEC_ADDV)))
|
||||||
|
(set (match_operand:DI 0 "register_operand" "=r")
|
||||||
|
(plus:DI (match_dup 1) (match_dup 2)))]
|
||||||
|
"TARGET_ARCH64"
|
||||||
|
"addcc\t%1, %2, %0"
|
||||||
|
[(set_attr "type" "compare")])
|
||||||
|
|
||||||
|
(define_insn "*cmp_ccv_plus_sltu_set"
|
||||||
|
[(set (reg:CCV CC_REG)
|
||||||
|
(compare:CCV (plus:SI (plus:SI (match_operand:SI 1 "register_operand" "%r")
|
||||||
|
(match_operand:SI 2 "arith_operand" "rI"))
|
||||||
|
(ltu:SI (reg:CCC CC_REG) (const_int 0)))
|
||||||
|
(unspec:SI [(plus:SI (match_dup 1) (match_dup 2))
|
||||||
|
(ltu:SI (reg:CCC CC_REG) (const_int 0))]
|
||||||
|
UNSPEC_ADDV)))
|
||||||
|
(set (match_operand:SI 0 "register_operand" "=r")
|
||||||
|
(plus:SI (plus:SI (match_dup 1) (match_dup 2))
|
||||||
|
(ltu:SI (reg:CCC CC_REG) (const_int 0))))]
|
||||||
|
""
|
||||||
|
"addxcc\t%1, %2, %0"
|
||||||
|
[(set_attr "type" "compare")])
|
||||||
|
|
||||||
|
|
||||||
(define_expand "subdi3"
|
(define_expand "subdi3"
|
||||||
[(set (match_operand:DI 0 "register_operand" "")
|
[(set (match_operand:DI 0 "register_operand" "")
|
||||||
(minus:DI (match_operand:DI 1 "register_operand" "")
|
(minus:DI (match_operand:DI 1 "register_operand" "")
|
||||||
|
|
@ -3890,6 +4111,56 @@
|
||||||
}
|
}
|
||||||
})
|
})
|
||||||
|
|
||||||
|
(define_expand "usubvdi4"
|
||||||
|
[(parallel [(set (reg:CCX CC_REG)
|
||||||
|
(compare:CCX (match_operand:DI 1 "register_or_zero_operand")
|
||||||
|
(match_operand:DI 2 "arith_add_operand")))
|
||||||
|
(set (match_operand:DI 0 "register_operand")
|
||||||
|
(minus:DI (match_dup 1) (match_dup 2)))])
|
||||||
|
(set (pc) (if_then_else (ltu (reg:CCX CC_REG) (const_int 0))
|
||||||
|
(label_ref (match_operand 3))
|
||||||
|
(pc)))]
|
||||||
|
""
|
||||||
|
{
|
||||||
|
if (operands[1] == const0_rtx)
|
||||||
|
{
|
||||||
|
emit_insn (gen_unegvdi3 (operands[0], operands[2], operands[3]));
|
||||||
|
DONE;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (!TARGET_64BIT)
|
||||||
|
{
|
||||||
|
emit_insn (gen_usubvdi4_sp32 (operands[0], operands[1], operands[2]));
|
||||||
|
rtx x = gen_rtx_LTU (VOIDmode, gen_rtx_REG (CCCmode, SPARC_ICC_REG),
|
||||||
|
const0_rtx);
|
||||||
|
emit_jump_insn (gen_cbranchcc4 (x, XEXP (x, 0), XEXP (x, 1), operands[3]));
|
||||||
|
DONE;
|
||||||
|
}
|
||||||
|
})
|
||||||
|
|
||||||
|
(define_expand "subvdi4"
|
||||||
|
[(parallel [(set (reg:CCXV CC_REG)
|
||||||
|
(compare:CCXV (minus:DI (match_operand:DI 1 "register_operand")
|
||||||
|
(match_operand:DI 2 "arith_add_operand"))
|
||||||
|
(unspec:DI [(match_dup 1) (match_dup 2)]
|
||||||
|
UNSPEC_SUBV)))
|
||||||
|
(set (match_operand:DI 0 "register_operand")
|
||||||
|
(minus:DI (match_dup 1) (match_dup 2)))])
|
||||||
|
(set (pc) (if_then_else (ne (reg:CCXV CC_REG) (const_int 0))
|
||||||
|
(label_ref (match_operand 3))
|
||||||
|
(pc)))]
|
||||||
|
""
|
||||||
|
{
|
||||||
|
if (!TARGET_64BIT)
|
||||||
|
{
|
||||||
|
emit_insn (gen_subvdi4_sp32 (operands[0], operands[1], operands[2]));
|
||||||
|
rtx x = gen_rtx_NE (VOIDmode, gen_rtx_REG (CCVmode, SPARC_ICC_REG),
|
||||||
|
const0_rtx);
|
||||||
|
emit_jump_insn (gen_cbranchcc4 (x, XEXP (x, 0), XEXP (x, 1), operands[3]));
|
||||||
|
DONE;
|
||||||
|
}
|
||||||
|
})
|
||||||
|
|
||||||
(define_insn_and_split "subdi3_sp32"
|
(define_insn_and_split "subdi3_sp32"
|
||||||
[(set (match_operand:DI 0 "register_operand" "=&r")
|
[(set (match_operand:DI 0 "register_operand" "=&r")
|
||||||
(minus:DI (match_operand:DI 1 "register_operand" "r")
|
(minus:DI (match_operand:DI 1 "register_operand" "r")
|
||||||
|
|
@ -3915,6 +4186,80 @@
|
||||||
}
|
}
|
||||||
[(set_attr "length" "2")])
|
[(set_attr "length" "2")])
|
||||||
|
|
||||||
|
(define_insn_and_split "usubvdi4_sp32"
|
||||||
|
[(set (reg:CCC CC_REG)
|
||||||
|
(compare:CCC (match_operand:DI 1 "register_operand" "r")
|
||||||
|
(match_operand:DI 2 "arith_double_operand" "rHI")))
|
||||||
|
(set (match_operand:DI 0 "register_operand" "=&r")
|
||||||
|
(minus:DI (match_dup 1) (match_dup 2)))]
|
||||||
|
"!TARGET_ARCH64"
|
||||||
|
"#"
|
||||||
|
"&& reload_completed"
|
||||||
|
[(parallel [(set (reg:CC CC_REG)
|
||||||
|
(compare:CC (match_dup 4) (match_dup 5)))
|
||||||
|
(set (match_dup 3)
|
||||||
|
(minus:SI (match_dup 4) (match_dup 5)))])
|
||||||
|
(parallel [(set (reg:CCC CC_REG)
|
||||||
|
(compare:CCC (zero_extend:DI
|
||||||
|
(minus:SI (minus:SI (match_dup 7)
|
||||||
|
(ltu:SI (reg:CC CC_REG)
|
||||||
|
(const_int 0)))
|
||||||
|
(match_dup 8)))
|
||||||
|
(minus:DI
|
||||||
|
(minus:DI (zero_extend:DI (match_dup 7))
|
||||||
|
(ltu:DI (reg:CC CC_REG)
|
||||||
|
(const_int 0)))
|
||||||
|
(zero_extend:DI (match_dup 8)))))
|
||||||
|
(set (match_dup 6)
|
||||||
|
(minus:SI (minus:SI (match_dup 7)
|
||||||
|
(ltu:SI (reg:CC CC_REG)
|
||||||
|
(const_int 0)))
|
||||||
|
(match_dup 8)))])]
|
||||||
|
{
|
||||||
|
operands[3] = gen_lowpart (SImode, operands[0]);
|
||||||
|
operands[4] = gen_lowpart (SImode, operands[1]);
|
||||||
|
operands[5] = gen_lowpart (SImode, operands[2]);
|
||||||
|
operands[6] = gen_highpart (SImode, operands[0]);
|
||||||
|
operands[7] = gen_highpart_mode (SImode, DImode, operands[1]);
|
||||||
|
operands[8] = gen_highpart_mode (SImode, DImode, operands[2]);
|
||||||
|
}
|
||||||
|
[(set_attr "length" "2")])
|
||||||
|
|
||||||
|
(define_insn_and_split "subvdi4_sp32"
|
||||||
|
[(set (reg:CCV CC_REG)
|
||||||
|
(compare:CCV (minus:DI (match_operand:DI 1 "register_operand" "%r")
|
||||||
|
(match_operand:DI 2 "arith_double_operand" "rHI"))
|
||||||
|
(unspec:DI [(match_dup 1) (match_dup 2)] UNSPEC_SUBV)))
|
||||||
|
(set (match_operand:DI 0 "register_operand" "=&r")
|
||||||
|
(minus:DI (match_dup 1) (match_dup 2)))]
|
||||||
|
"!TARGET_ARCH64"
|
||||||
|
"#"
|
||||||
|
"&& reload_completed"
|
||||||
|
[(parallel [(set (reg:CC CC_REG)
|
||||||
|
(compare:CC (match_dup 4) (match_dup 5)))
|
||||||
|
(set (match_dup 3)
|
||||||
|
(minus:SI (match_dup 4) (match_dup 5)))])
|
||||||
|
(parallel [(set (reg:CCV CC_REG)
|
||||||
|
(compare:CCV (minus:SI (minus:SI (match_dup 7) (match_dup 8))
|
||||||
|
(ltu:SI (reg:CC CC_REG)
|
||||||
|
(const_int 0)))
|
||||||
|
(unspec:SI [(minus:SI (match_dup 7) (match_dup 8))
|
||||||
|
(ltu:SI (reg:CC CC_REG)
|
||||||
|
(const_int 0))]
|
||||||
|
UNSPEC_SUBV)))
|
||||||
|
(set (match_dup 6)
|
||||||
|
(minus:SI (minus:SI (match_dup 7) (match_dup 8))
|
||||||
|
(ltu:SI (reg:CC CC_REG) (const_int 0))))])]
|
||||||
|
{
|
||||||
|
operands[3] = gen_lowpart (SImode, operands[0]);
|
||||||
|
operands[4] = gen_lowpart (SImode, operands[1]);
|
||||||
|
operands[5] = gen_lowpart (SImode, operands[2]);
|
||||||
|
operands[6] = gen_highpart (SImode, operands[0]);
|
||||||
|
operands[7] = gen_highpart_mode (SImode, DImode, operands[1]);
|
||||||
|
operands[8] = gen_highpart_mode (SImode, DImode, operands[2]);
|
||||||
|
}
|
||||||
|
[(set_attr "length" "2")])
|
||||||
|
|
||||||
(define_insn_and_split "*subx_extend_sp32"
|
(define_insn_and_split "*subx_extend_sp32"
|
||||||
[(set (match_operand:DI 0 "register_operand" "=r")
|
[(set (match_operand:DI 0 "register_operand" "=r")
|
||||||
(zero_extend:DI (minus:SI (minus:SI
|
(zero_extend:DI (minus:SI (minus:SI
|
||||||
|
|
@ -3971,6 +4316,37 @@
|
||||||
[(set_attr "type" "*,*")
|
[(set_attr "type" "*,*")
|
||||||
(set_attr "fptype" "*,*")])
|
(set_attr "fptype" "*,*")])
|
||||||
|
|
||||||
|
(define_expand "usubvsi4"
|
||||||
|
[(parallel [(set (reg:CC CC_REG)
|
||||||
|
(compare:CC (match_operand:SI 1 "register_or_zero_operand")
|
||||||
|
(match_operand:SI 2 "arith_operand")))
|
||||||
|
(set (match_operand:SI 0 "register_operand")
|
||||||
|
(minus:SI (match_dup 1) (match_dup 2)))])
|
||||||
|
(set (pc) (if_then_else (ltu (reg:CC CC_REG) (const_int 0))
|
||||||
|
(label_ref (match_operand 3))
|
||||||
|
(pc)))]
|
||||||
|
""
|
||||||
|
{
|
||||||
|
if (operands[1] == const0_rtx)
|
||||||
|
{
|
||||||
|
emit_insn (gen_unegvsi3 (operands[0], operands[2], operands[3]));
|
||||||
|
DONE;
|
||||||
|
}
|
||||||
|
})
|
||||||
|
|
||||||
|
(define_expand "subvsi4"
|
||||||
|
[(parallel [(set (reg:CCV CC_REG)
|
||||||
|
(compare:CCV (minus:SI (match_operand:SI 1 "register_operand")
|
||||||
|
(match_operand:SI 2 "arith_operand"))
|
||||||
|
(unspec:SI [(match_dup 1) (match_dup 2)]
|
||||||
|
UNSPEC_SUBV)))
|
||||||
|
(set (match_operand:SI 0 "register_operand")
|
||||||
|
(minus:SI (match_dup 1) (match_dup 2)))])
|
||||||
|
(set (pc) (if_then_else (ne (reg:CCV CC_REG) (const_int 0))
|
||||||
|
(label_ref (match_operand 3))
|
||||||
|
(pc)))]
|
||||||
|
"")
|
||||||
|
|
||||||
(define_insn "*cmp_ccnz_minus"
|
(define_insn "*cmp_ccnz_minus"
|
||||||
[(set (reg:CCNZ CC_REG)
|
[(set (reg:CCNZ CC_REG)
|
||||||
(compare:CCNZ (minus:SI (match_operand:SI 0 "register_or_zero_operand" "rJ")
|
(compare:CCNZ (minus:SI (match_operand:SI 0 "register_or_zero_operand" "rJ")
|
||||||
|
|
@ -4031,6 +4407,82 @@
|
||||||
"subcc\t%r1, %2, %0"
|
"subcc\t%r1, %2, %0"
|
||||||
[(set_attr "type" "compare")])
|
[(set_attr "type" "compare")])
|
||||||
|
|
||||||
|
(define_insn "*cmp_ccc_minus_sltu_set"
|
||||||
|
[(set (reg:CCC CC_REG)
|
||||||
|
(compare:CCC (zero_extend:DI
|
||||||
|
(minus:SI
|
||||||
|
(minus:SI
|
||||||
|
(match_operand:SI 1 "register_or_zero_operand" "rJ")
|
||||||
|
(ltu:SI (reg:CC CC_REG) (const_int 0)))
|
||||||
|
(match_operand:SI 2 "arith_operand" "rI")))
|
||||||
|
(minus:DI
|
||||||
|
(minus:DI
|
||||||
|
(zero_extend:DI (match_dup 1))
|
||||||
|
(ltu:DI (reg:CC CC_REG) (const_int 0)))
|
||||||
|
(zero_extend:DI (match_dup 2)))))
|
||||||
|
(set (match_operand:SI 0 "register_operand" "=r")
|
||||||
|
(minus:SI (minus:SI (match_dup 1)
|
||||||
|
(ltu:SI (reg:CC CC_REG) (const_int 0)))
|
||||||
|
(match_dup 2)))]
|
||||||
|
""
|
||||||
|
"subxcc\t%r1, %2, %0"
|
||||||
|
[(set_attr "type" "compare")])
|
||||||
|
|
||||||
|
(define_insn "*cmp_ccv_minus"
|
||||||
|
[(set (reg:CCV CC_REG)
|
||||||
|
(compare:CCV (minus:SI (match_operand:SI 0 "register_or_zero_operand" "rJ")
|
||||||
|
(match_operand:SI 1 "arith_operand" "rI"))
|
||||||
|
(unspec:SI [(match_dup 0) (match_dup 1)] UNSPEC_SUBV)))]
|
||||||
|
""
|
||||||
|
"subcc\t%r0, %1, %%g0"
|
||||||
|
[(set_attr "type" "compare")])
|
||||||
|
|
||||||
|
(define_insn "*cmp_ccxv_minus"
|
||||||
|
[(set (reg:CCXV CC_REG)
|
||||||
|
(compare:CCXV (minus:DI (match_operand:DI 0 "register_or_zero_operand" "rJ")
|
||||||
|
(match_operand:DI 1 "arith_operand" "rI"))
|
||||||
|
(unspec:DI [(match_dup 0) (match_dup 1)] UNSPEC_SUBV)))]
|
||||||
|
"TARGET_ARCH64"
|
||||||
|
"subcc\t%r0, %1, %%g0"
|
||||||
|
[(set_attr "type" "compare")])
|
||||||
|
|
||||||
|
(define_insn "*cmp_ccv_minus_set"
|
||||||
|
[(set (reg:CCV CC_REG)
|
||||||
|
(compare:CCV (minus:SI (match_operand:SI 1 "register_or_zero_operand" "rJ")
|
||||||
|
(match_operand:SI 2 "arith_operand" "rI"))
|
||||||
|
(unspec:SI [(match_dup 1) (match_dup 2)] UNSPEC_SUBV)))
|
||||||
|
(set (match_operand:SI 0 "register_operand" "=r")
|
||||||
|
(minus:SI (match_dup 1) (match_dup 2)))]
|
||||||
|
""
|
||||||
|
"subcc\t%r1, %2, %0"
|
||||||
|
[(set_attr "type" "compare")])
|
||||||
|
|
||||||
|
(define_insn "*cmp_ccxv_minus_set"
|
||||||
|
[(set (reg:CCXV CC_REG)
|
||||||
|
(compare:CCXV (minus:DI (match_operand:DI 1 "register_or_zero_operand" "rJ")
|
||||||
|
(match_operand:DI 2 "arith_operand" "rI"))
|
||||||
|
(unspec:DI [(match_dup 1) (match_dup 2)] UNSPEC_SUBV)))
|
||||||
|
(set (match_operand:DI 0 "register_operand" "=r")
|
||||||
|
(minus:DI (match_dup 1) (match_dup 2)))]
|
||||||
|
"TARGET_ARCH64"
|
||||||
|
"subcc\t%r1, %2, %0"
|
||||||
|
[(set_attr "type" "compare")])
|
||||||
|
|
||||||
|
(define_insn "*cmp_ccv_minus_sltu_set"
|
||||||
|
[(set (reg:CCV CC_REG)
|
||||||
|
(compare:CCV (minus:SI (minus:SI (match_operand:SI 1 "register_or_zero_operand" "rJ")
|
||||||
|
(match_operand:SI 2 "arith_operand" "rI"))
|
||||||
|
(ltu:SI (reg:CC CC_REG) (const_int 0)))
|
||||||
|
(unspec:SI [(minus:SI (match_dup 1) (match_dup 2))
|
||||||
|
(ltu:SI (reg:CC CC_REG) (const_int 0))]
|
||||||
|
UNSPEC_SUBV)))
|
||||||
|
(set (match_operand:SI 0 "register_operand" "=r")
|
||||||
|
(minus:SI (minus:SI (match_dup 1) (match_dup 2))
|
||||||
|
(ltu:SI (reg:CC CC_REG) (const_int 0))))]
|
||||||
|
""
|
||||||
|
"subxcc\t%1, %2, %0"
|
||||||
|
[(set_attr "type" "compare")])
|
||||||
|
|
||||||
|
|
||||||
;; Integer multiply/divide instructions.
|
;; Integer multiply/divide instructions.
|
||||||
|
|
||||||
|
|
@ -5127,6 +5579,50 @@
|
||||||
}
|
}
|
||||||
})
|
})
|
||||||
|
|
||||||
|
(define_expand "unegvdi3"
|
||||||
|
[(parallel [(set (reg:CCXC CC_REG)
|
||||||
|
(compare:CCXC (not:DI (match_operand:DI 1 "register_operand" ""))
|
||||||
|
(const_int -1)))
|
||||||
|
(set (match_operand:DI 0 "register_operand" "")
|
||||||
|
(neg:DI (match_dup 1)))])
|
||||||
|
(set (pc)
|
||||||
|
(if_then_else (ltu (reg:CCXC CC_REG) (const_int 0))
|
||||||
|
(label_ref (match_operand 2 ""))
|
||||||
|
(pc)))]
|
||||||
|
""
|
||||||
|
{
|
||||||
|
if (!TARGET_64BIT)
|
||||||
|
{
|
||||||
|
emit_insn (gen_unegvdi3_sp32 (operands[0], operands[1]));
|
||||||
|
rtx x = gen_rtx_LTU (VOIDmode, gen_rtx_REG (CCCmode, SPARC_ICC_REG),
|
||||||
|
const0_rtx);
|
||||||
|
emit_jump_insn (gen_cbranchcc4 (x, XEXP (x, 0), XEXP (x, 1), operands[2]));
|
||||||
|
DONE;
|
||||||
|
}
|
||||||
|
})
|
||||||
|
|
||||||
|
(define_expand "negvdi3"
|
||||||
|
[(parallel [(set (reg:CCXV CC_REG)
|
||||||
|
(compare:CCXV (neg:DI (match_operand:DI 1 "register_operand" ""))
|
||||||
|
(unspec:DI [(match_dup 1)] UNSPEC_NEGV)))
|
||||||
|
(set (match_operand:DI 0 "register_operand" "")
|
||||||
|
(neg:DI (match_dup 1)))])
|
||||||
|
(set (pc)
|
||||||
|
(if_then_else (ne (reg:CCXV CC_REG) (const_int 0))
|
||||||
|
(label_ref (match_operand 2 ""))
|
||||||
|
(pc)))]
|
||||||
|
""
|
||||||
|
{
|
||||||
|
if (!TARGET_64BIT)
|
||||||
|
{
|
||||||
|
emit_insn (gen_negvdi3_sp32 (operands[0], operands[1]));
|
||||||
|
rtx x = gen_rtx_NE (VOIDmode, gen_rtx_REG (CCVmode, SPARC_ICC_REG),
|
||||||
|
const0_rtx);
|
||||||
|
emit_jump_insn (gen_cbranchcc4 (x, XEXP (x, 0), XEXP (x, 1), operands[2]));
|
||||||
|
DONE;
|
||||||
|
}
|
||||||
|
})
|
||||||
|
|
||||||
(define_insn_and_split "negdi2_sp32"
|
(define_insn_and_split "negdi2_sp32"
|
||||||
[(set (match_operand:DI 0 "register_operand" "=&r")
|
[(set (match_operand:DI 0 "register_operand" "=&r")
|
||||||
(neg:DI (match_operand:DI 1 "register_operand" "r")))
|
(neg:DI (match_operand:DI 1 "register_operand" "r")))
|
||||||
|
|
@ -5145,6 +5641,64 @@
|
||||||
operands[5] = gen_lowpart (SImode, operands[1]);"
|
operands[5] = gen_lowpart (SImode, operands[1]);"
|
||||||
[(set_attr "length" "2")])
|
[(set_attr "length" "2")])
|
||||||
|
|
||||||
|
(define_insn_and_split "unegvdi3_sp32"
|
||||||
|
[(set (reg:CCC CC_REG)
|
||||||
|
(compare:CCC (not:DI (match_operand:DI 1 "register_operand" "r"))
|
||||||
|
(const_int -1)))
|
||||||
|
(set (match_operand:DI 0 "register_operand" "=&r")
|
||||||
|
(neg:DI (match_dup 1)))]
|
||||||
|
"!TARGET_ARCH64"
|
||||||
|
"#"
|
||||||
|
"&& reload_completed"
|
||||||
|
[(parallel [(set (reg:CCC CC_REG)
|
||||||
|
(compare:CCC (not:SI (match_dup 5)) (const_int -1)))
|
||||||
|
(set (match_dup 4) (neg:SI (match_dup 5)))])
|
||||||
|
(parallel [(set (reg:CCC CC_REG)
|
||||||
|
(compare:CCC (zero_extend:DI
|
||||||
|
(neg:SI (plus:SI (match_dup 3)
|
||||||
|
(ltu:SI (reg:CCC CC_REG)
|
||||||
|
(const_int 0)))))
|
||||||
|
(neg:DI (plus:DI (zero_extend:DI (match_dup 3))
|
||||||
|
(ltu:DI (reg:CCC CC_REG)
|
||||||
|
(const_int 0))))))
|
||||||
|
(set (match_dup 2) (neg:SI (plus:SI (match_dup 3)
|
||||||
|
(ltu:SI (reg:CCC CC_REG)
|
||||||
|
(const_int 0)))))])]
|
||||||
|
"operands[2] = gen_highpart (SImode, operands[0]);
|
||||||
|
operands[3] = gen_highpart (SImode, operands[1]);
|
||||||
|
operands[4] = gen_lowpart (SImode, operands[0]);
|
||||||
|
operands[5] = gen_lowpart (SImode, operands[1]);"
|
||||||
|
[(set_attr "length" "2")])
|
||||||
|
|
||||||
|
(define_insn_and_split "negvdi3_sp32"
|
||||||
|
[(set (reg:CCV CC_REG)
|
||||||
|
(compare:CCV (neg:DI (match_operand:DI 1 "register_operand" "r"))
|
||||||
|
(unspec:DI [(match_dup 1)] UNSPEC_NEGV)))
|
||||||
|
(set (match_operand:DI 0 "register_operand" "=&r")
|
||||||
|
(neg:DI (match_dup 1)))]
|
||||||
|
"!TARGET_ARCH64"
|
||||||
|
"#"
|
||||||
|
"&& reload_completed"
|
||||||
|
[(parallel [(set (reg:CCC CC_REG)
|
||||||
|
(compare:CCC (not:SI (match_dup 5)) (const_int -1)))
|
||||||
|
(set (match_dup 4) (neg:SI (match_dup 5)))])
|
||||||
|
(parallel [(set (reg:CCV CC_REG)
|
||||||
|
(compare:CCV (neg:SI (plus:SI (match_dup 3)
|
||||||
|
(ltu:SI (reg:CCC CC_REG)
|
||||||
|
(const_int 0))))
|
||||||
|
(unspec:SI [(plus:SI (match_dup 3)
|
||||||
|
(ltu:SI (reg:CCC CC_REG)
|
||||||
|
(const_int 0)))]
|
||||||
|
UNSPEC_NEGV)))
|
||||||
|
(set (match_dup 2) (neg:SI (plus:SI (match_dup 3)
|
||||||
|
(ltu:SI (reg:CCC CC_REG)
|
||||||
|
(const_int 0)))))])]
|
||||||
|
"operands[2] = gen_highpart (SImode, operands[0]);
|
||||||
|
operands[3] = gen_highpart (SImode, operands[1]);
|
||||||
|
operands[4] = gen_lowpart (SImode, operands[0]);
|
||||||
|
operands[5] = gen_lowpart (SImode, operands[1]);"
|
||||||
|
[(set_attr "length" "2")])
|
||||||
|
|
||||||
(define_insn "*negdi2_sp64"
|
(define_insn "*negdi2_sp64"
|
||||||
[(set (match_operand:DI 0 "register_operand" "=r")
|
[(set (match_operand:DI 0 "register_operand" "=r")
|
||||||
(neg:DI (match_operand:DI 1 "register_operand" "r")))]
|
(neg:DI (match_operand:DI 1 "register_operand" "r")))]
|
||||||
|
|
@ -5157,6 +5711,30 @@
|
||||||
""
|
""
|
||||||
"sub\t%%g0, %1, %0")
|
"sub\t%%g0, %1, %0")
|
||||||
|
|
||||||
|
(define_expand "unegvsi3"
|
||||||
|
[(parallel [(set (reg:CCC CC_REG)
|
||||||
|
(compare:CCC (not:SI (match_operand:SI 1 "arith_operand" ""))
|
||||||
|
(const_int -1)))
|
||||||
|
(set (match_operand:SI 0 "register_operand" "")
|
||||||
|
(neg:SI (match_dup 1)))])
|
||||||
|
(set (pc)
|
||||||
|
(if_then_else (ltu (reg:CCC CC_REG) (const_int 0))
|
||||||
|
(label_ref (match_operand 2 ""))
|
||||||
|
(pc)))]
|
||||||
|
"")
|
||||||
|
|
||||||
|
(define_expand "negvsi3"
|
||||||
|
[(parallel [(set (reg:CCV CC_REG)
|
||||||
|
(compare:CCV (neg:SI (match_operand:SI 1 "arith_operand" ""))
|
||||||
|
(unspec:SI [(match_dup 1)] UNSPEC_NEGV)))
|
||||||
|
(set (match_operand:SI 0 "register_operand" "")
|
||||||
|
(neg:SI (match_dup 1)))])
|
||||||
|
(set (pc)
|
||||||
|
(if_then_else (ne (reg:CCV CC_REG) (const_int 0))
|
||||||
|
(label_ref (match_operand 2 ""))
|
||||||
|
(pc)))]
|
||||||
|
"")
|
||||||
|
|
||||||
(define_insn "*cmp_ccnz_neg"
|
(define_insn "*cmp_ccnz_neg"
|
||||||
[(set (reg:CCNZ CC_REG)
|
[(set (reg:CCNZ CC_REG)
|
||||||
(compare:CCNZ (neg:SI (match_operand:SI 0 "arith_operand" "rI"))
|
(compare:CCNZ (neg:SI (match_operand:SI 0 "arith_operand" "rI"))
|
||||||
|
|
@ -5213,6 +5791,73 @@
|
||||||
"subcc\t%%g0, %1, %0"
|
"subcc\t%%g0, %1, %0"
|
||||||
[(set_attr "type" "compare")])
|
[(set_attr "type" "compare")])
|
||||||
|
|
||||||
|
(define_insn "*cmp_ccc_neg_sltu_set"
|
||||||
|
[(set (reg:CCC CC_REG)
|
||||||
|
(compare:CCC (zero_extend:DI
|
||||||
|
(neg:SI (plus:SI (match_operand:SI 1 "arith_operand" "rI")
|
||||||
|
(ltu:SI (reg:CCC CC_REG)
|
||||||
|
(const_int 0)))))
|
||||||
|
(neg:DI (plus:DI (zero_extend:DI (match_dup 1))
|
||||||
|
(ltu:DI (reg:CCC CC_REG)
|
||||||
|
(const_int 0))))))
|
||||||
|
(set (match_operand:SI 0 "register_operand" "=r")
|
||||||
|
(neg:SI (plus:SI (match_dup 1)
|
||||||
|
(ltu:SI (reg:CCC CC_REG) (const_int 0)))))]
|
||||||
|
""
|
||||||
|
"subxcc\t%%g0, %1, %0"
|
||||||
|
[(set_attr "type" "compare")])
|
||||||
|
|
||||||
|
(define_insn "*cmp_ccv_neg"
|
||||||
|
[(set (reg:CCV CC_REG)
|
||||||
|
(compare:CCV (neg:SI (match_operand:SI 0 "arith_operand" "rI"))
|
||||||
|
(unspec:SI [(match_dup 0)] UNSPEC_NEGV)))]
|
||||||
|
""
|
||||||
|
"subcc\t%%g0, %0, %%g0"
|
||||||
|
[(set_attr "type" "compare")])
|
||||||
|
|
||||||
|
(define_insn "*cmp_ccxv_neg"
|
||||||
|
[(set (reg:CCXV CC_REG)
|
||||||
|
(compare:CCXV (neg:DI (match_operand:DI 0 "arith_operand" "rI"))
|
||||||
|
(unspec:DI [(match_dup 0)] UNSPEC_NEGV)))]
|
||||||
|
"TARGET_ARCH64"
|
||||||
|
"subcc\t%%g0, %0, %%g0"
|
||||||
|
[(set_attr "type" "compare")])
|
||||||
|
|
||||||
|
(define_insn "*cmp_ccv_neg_set"
|
||||||
|
[(set (reg:CCV CC_REG)
|
||||||
|
(compare:CCV (neg:SI (match_operand:SI 1 "arith_operand" "rI"))
|
||||||
|
(unspec:SI [(match_dup 1)] UNSPEC_NEGV)))
|
||||||
|
(set (match_operand:SI 0 "register_operand" "=r")
|
||||||
|
(neg:SI (match_dup 1)))]
|
||||||
|
""
|
||||||
|
"subcc\t%%g0, %1, %0"
|
||||||
|
[(set_attr "type" "compare")])
|
||||||
|
|
||||||
|
(define_insn "*cmp_ccxv_neg_set"
|
||||||
|
[(set (reg:CCXV CC_REG)
|
||||||
|
(compare:CCXV (neg:DI (match_operand:DI 1 "arith_operand" "rI"))
|
||||||
|
(unspec:DI [(match_dup 1)] UNSPEC_NEGV)))
|
||||||
|
(set (match_operand:DI 0 "register_operand" "=r")
|
||||||
|
(neg:DI (match_dup 1)))]
|
||||||
|
"TARGET_ARCH64"
|
||||||
|
"subcc\t%%g0, %1, %0"
|
||||||
|
[(set_attr "type" "compare")])
|
||||||
|
|
||||||
|
(define_insn "*cmp_ccv_neg_sltu_set"
|
||||||
|
[(set (reg:CCV CC_REG)
|
||||||
|
(compare:CCV (neg:SI (plus:SI (match_operand:SI 1 "arith_operand" "rI")
|
||||||
|
(ltu:SI (reg:CCC CC_REG) (const_int 0))))
|
||||||
|
(unspec:SI [(plus:SI (match_dup 1)
|
||||||
|
(ltu:SI (reg:CCC CC_REG)
|
||||||
|
(const_int 0)))]
|
||||||
|
UNSPEC_NEGV)))
|
||||||
|
(set (match_operand:SI 0 "register_operand" "=r")
|
||||||
|
(neg:SI (plus:SI (match_dup 1)
|
||||||
|
(ltu:SI (reg:CCC CC_REG) (const_int 0)))))]
|
||||||
|
""
|
||||||
|
"subxcc\t%%g0, %1, %0"
|
||||||
|
[(set_attr "type" "compare")])
|
||||||
|
|
||||||
|
|
||||||
(define_insn "one_cmpldi2"
|
(define_insn "one_cmpldi2"
|
||||||
[(set (match_operand:DI 0 "register_operand" "=r")
|
[(set (match_operand:DI 0 "register_operand" "=r")
|
||||||
|
|
|
||||||
|
|
@ -1,3 +1,9 @@
|
||||||
|
2016-10-21 Eric Botcazou <ebotcazou@adacore.com>
|
||||||
|
|
||||||
|
* gcc.target/sparc/overflow-1.c: New test.
|
||||||
|
* gcc.target/sparc/overflow-2.c: Likewise.
|
||||||
|
* gcc.target/sparc/overflow-3.c: Likewise.
|
||||||
|
|
||||||
2016-10-21 Andre Vieira <andre.simoesdiasvieira@arm.com>
|
2016-10-21 Andre Vieira <andre.simoesdiasvieira@arm.com>
|
||||||
|
|
||||||
* gcc.target/arm/pure-code/pure-code.exp: Require arm_cortex_m
|
* gcc.target/arm/pure-code/pure-code.exp: Require arm_cortex_m
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,43 @@
|
||||||
|
/* { dg-do compile } */
|
||||||
|
/* { dg-options "-O -mcpu=v8" } */
|
||||||
|
/* { dg-require-effective-target ilp32 } */
|
||||||
|
|
||||||
|
#include <stdbool.h>
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
bool my_uadd_overflow (uint32_t a, uint32_t b, uint32_t *res)
|
||||||
|
{
|
||||||
|
return __builtin_add_overflow (a, b, res);
|
||||||
|
}
|
||||||
|
|
||||||
|
bool my_usub_overflow (uint32_t a, uint32_t b, uint32_t *res)
|
||||||
|
{
|
||||||
|
return __builtin_sub_overflow (a, b, res);
|
||||||
|
}
|
||||||
|
|
||||||
|
bool my_uneg_overflow (uint32_t a, uint32_t *res)
|
||||||
|
{
|
||||||
|
return __builtin_sub_overflow (0, a, res);
|
||||||
|
}
|
||||||
|
|
||||||
|
bool my_add_overflow (int32_t a, int32_t b, int32_t *res)
|
||||||
|
{
|
||||||
|
return __builtin_add_overflow (a, b, res);
|
||||||
|
}
|
||||||
|
|
||||||
|
bool my_sub_overflow (int32_t a, int32_t b, int32_t *res)
|
||||||
|
{
|
||||||
|
return __builtin_sub_overflow (a, b, res);
|
||||||
|
}
|
||||||
|
|
||||||
|
bool my_neg_overflow (int32_t a, int32_t *res)
|
||||||
|
{
|
||||||
|
return __builtin_sub_overflow (0, a, res);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* { dg-final { scan-assembler-times "addcc\t%" 2 } } */
|
||||||
|
/* { dg-final { scan-assembler-times "subcc\t%" 4 } } */
|
||||||
|
/* { dg-final { scan-assembler-times "addx\t%" 3 } } */
|
||||||
|
/* { dg-final { scan-assembler-times "bvs" 3 } } */
|
||||||
|
/* { dg-final { scan-assembler-not "cmp\t%" } } */
|
||||||
|
/* { dg-final { scan-assembler-not "save\t%" } } */
|
||||||
|
|
@ -0,0 +1,46 @@
|
||||||
|
/* { dg-do compile } */
|
||||||
|
/* { dg-options "-O -mcpu=v8" } */
|
||||||
|
/* { dg-require-effective-target ilp32 } */
|
||||||
|
|
||||||
|
#include <stdbool.h>
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
bool my_uadd_overflow (uint64_t a, uint64_t b, uint64_t *res)
|
||||||
|
{
|
||||||
|
return __builtin_add_overflow (a, b, res);
|
||||||
|
}
|
||||||
|
|
||||||
|
bool my_usub_overflow (uint64_t a, uint64_t b, uint64_t *res)
|
||||||
|
{
|
||||||
|
return __builtin_sub_overflow (a, b, res);
|
||||||
|
}
|
||||||
|
|
||||||
|
bool my_uneg_overflow (uint64_t a, uint64_t *res)
|
||||||
|
{
|
||||||
|
return __builtin_sub_overflow (0, a, res);
|
||||||
|
}
|
||||||
|
|
||||||
|
bool my_add_overflow (int64_t a, int64_t b, int64_t *res)
|
||||||
|
{
|
||||||
|
return __builtin_add_overflow (a, b, res);
|
||||||
|
}
|
||||||
|
|
||||||
|
bool my_sub_overflow (int64_t a, int64_t b, int64_t *res)
|
||||||
|
{
|
||||||
|
return __builtin_sub_overflow (a, b, res);
|
||||||
|
}
|
||||||
|
|
||||||
|
bool my_neg_overflow (int64_t a, int64_t *res)
|
||||||
|
{
|
||||||
|
return __builtin_sub_overflow (0, a, res);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* { dg-final { scan-assembler-times "addcc\t%" 2 } } */
|
||||||
|
/* { dg-final { scan-assembler-times "addxcc\t%" 2 } } */
|
||||||
|
/* { dg-final { scan-assembler-times "subcc\t%" 4 } } */
|
||||||
|
/* { dg-final { scan-assembler-times "subxcc\t%" 4 } } */
|
||||||
|
/* { dg-final { scan-assembler-times "addx\t%" 2 } } */
|
||||||
|
/* { dg-final { scan-assembler-times "blu" 1 } } */
|
||||||
|
/* { dg-final { scan-assembler-times "bvs" 3 } } */
|
||||||
|
/* { dg-final { scan-assembler-not "cmp\t%" } } */
|
||||||
|
/* { dg-final { scan-assembler-not "save\t%" } } */
|
||||||
|
|
@ -0,0 +1,44 @@
|
||||||
|
/* { dg-do compile } */
|
||||||
|
/* { dg-options "-O" } */
|
||||||
|
/* { dg-require-effective-target lp64 } */
|
||||||
|
|
||||||
|
#include <stdbool.h>
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
bool my_uadd_overflow (uint64_t a, uint64_t b, uint64_t *res)
|
||||||
|
{
|
||||||
|
return __builtin_add_overflow (a, b, res);
|
||||||
|
}
|
||||||
|
|
||||||
|
bool my_usub_overflow (uint64_t a, uint64_t b, uint64_t *res)
|
||||||
|
{
|
||||||
|
return __builtin_sub_overflow (a, b, res);
|
||||||
|
}
|
||||||
|
|
||||||
|
bool my_uneg_overflow (uint64_t a, uint64_t *res)
|
||||||
|
{
|
||||||
|
return __builtin_sub_overflow (0, a, res);
|
||||||
|
}
|
||||||
|
|
||||||
|
bool my_add_overflow (int64_t a, int64_t b, int64_t *res)
|
||||||
|
{
|
||||||
|
return __builtin_add_overflow (a, b, res);
|
||||||
|
}
|
||||||
|
|
||||||
|
bool my_sub_overflow (int64_t a, int64_t b, int64_t *res)
|
||||||
|
{
|
||||||
|
return __builtin_sub_overflow (a, b, res);
|
||||||
|
}
|
||||||
|
|
||||||
|
bool my_neg_overflow (int64_t a, int64_t *res)
|
||||||
|
{
|
||||||
|
return __builtin_sub_overflow (0, a, res);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* { dg-final { scan-assembler-times "addcc\t%" 2 } } */
|
||||||
|
/* { dg-final { scan-assembler-times "subcc\t%" 4 } } */
|
||||||
|
/* { dg-final { scan-assembler-times "movlu\t%" 1 } } */
|
||||||
|
/* { dg-final { scan-assembler-times "blu" 2 } } */
|
||||||
|
/* { dg-final { scan-assembler-times "bvs" 3 } } */
|
||||||
|
/* { dg-final { scan-assembler-not "cmp\t%" } } */
|
||||||
|
/* { dg-final { scan-assembler-not "save\t%" } } */
|
||||||
Loading…
Reference in New Issue