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md.texi (Machine Constraints): Correct formatting in PDP-11 constraints. 

* doc/md.texi (Machine Constraints): Correct formatting in PDP-11
constraints.

From-SVN: r166346
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Paul Koning 2010-11-04 21:01:59 -04:00 committed by Paul Koning
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@ -1,3 +1,8 @@
2010-11-04 Paul Koning <ni1d@arrl.net>
* doc/md.texi (Machine Constraints): Correct formatting in PDP-11
constraints.
2010-11-04 Chao-ying Fu <fu@mips.com> 2010-11-04 Chao-ying Fu <fu@mips.com>
* configure.ac: Test assembler support for DSP Rev1 mult. * configure.ac: Test assembler support for DSP Rev1 mult.

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gcc/doc/md.texi
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@ -2928,8 +2928,8 @@ Floating point registers AC0 through AC3. These can be loaded from/to
memory with a single instruction. memory with a single instruction.
@item d @item d
Odd numbered general registers (R1, R3, R5). These are used for 16 Odd numbered general registers (R1, R3, R5). These are used for
bit multiply operations. 16-bit multiply operations.
@item f @item f
Any of the floating point registers (AC0 through AC5). Any of the floating point registers (AC0 through AC5).
@ -2951,13 +2951,13 @@ An integer constant that does not meet the constraints for codes
The integer constant 1. The integer constant 1.
@item M @item M
The integer constant -1. The integer constant @minus{}1.
@item N @item N
The integer constant 0. The integer constant 0.
@item O @item O
Integer constants -4 through -1 and 1 through 4; shifts by these Integer constants @minus{}4 through @minus{}1 and 1 through 4; shifts by these
amounts are handled as multiple single-bit shifts rather than a single amounts are handled as multiple single-bit shifts rather than a single
variable-length shift. variable-length shift.