mirror of git://gcc.gnu.org/git/gcc.git
alpha.md (vecmodesuffix): New mode attribute.
* config/alpha/alpha.md (vecmodesuffix): New mode attribute.
(modesuffix): Handle V8QI and V4HI modes.
(any_maxmin): New code iterator.
(maxmin): New code attribute.
(<code><mode>3): Macroize insn from {smax,smin,umax,umin}{qi,hi}3
using any_maxmin code iterator and I12MODE mode iterator.
(<code><mode>3): Macroize insn from {smax,smin,umax,umin}{v8qi,v4hi}3
using any_maxmin code iterator and VEC12 mode iterator.
From-SVN: r192396
This commit is contained in:
Uros Bizjak
Uros Bizjak
parent
3b06f98418
commit
87218838b8
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@ -1,3 +1,14 @@
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2012-10-12 Uros Bizjak <ubizjak@gmail.com>
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* config/alpha/alpha.md (vecmodesuffix): New mode attribute.
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(modesuffix): Handle V8QI and V4HI modes.
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(any_maxmin): New code iterator.
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(maxmin): New code attribute.
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(<code><mode>3): Macroize insn from {smax,smin,umax,umin}{qi,hi}3
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using any_maxmin code iterator and I12MODE mode iterator.
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(<code><mode>3): Macroize insn from {smax,smin,umax,umin}{v8qi,v4hi}3
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using any_maxmin code iterator and VEC12 mode iterator.
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2012-10-12 Marc Glisse <marc.glisse@inria.fr>
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* optabs.c (vector_compare_rtx): Change prototype.
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@ -62,7 +73,7 @@
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*mov{qi,hi,si,di}cc_lbc using IMODE mode iterator.
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(*mov<mode>cc_lbs): Macroize insn from
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*mov{qi,hi,si,di}cc_lbs using IMODE mode iterator.
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(mov<mode>cc): Macroize insn from mov{si,di}cc_lbs
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(mov<mode>cc): Macroize expander from mov{si,di}cc
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using I48MODE mode iterator.
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2012-10-11 Steven Bosscher <steven@gcc.gnu.org>
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@ -95,8 +95,16 @@
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(define_mode_iterator I124MODE [QI HI SI])
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(define_mode_iterator I248MODE [HI SI DI])
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(define_mode_iterator I48MODE [SI DI])
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(define_mode_attr DWI [(SI "DI") (DI "TI")])
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(define_mode_attr modesuffix [(QI "b") (HI "w") (SI "l") (DI "q")])
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(define_mode_attr modesuffix [(QI "b") (HI "w") (SI "l") (DI "q")
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(V8QI "b8") (V4HI "w4")])
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(define_mode_attr vecmodesuffix [(QI "b8") (HI "w4")])
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(define_code_iterator any_maxmin [smax smin umax umin])
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(define_code_attr maxmin [(smax "maxs") (smin "mins")
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(umax "maxu") (umin "minu")])
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;; Where necessary, the suffixes _le and _be are used to distinguish between
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;; little-endian and big-endian patterns.
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@ -2723,68 +2731,13 @@
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(match_dup 0) (match_dup 1)))]
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"")
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(define_insn "sminqi3"
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[(set (match_operand:QI 0 "register_operand" "=r")
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(smin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
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(match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
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(define_insn "<code><mode>3"
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[(set (match_operand:I12MODE 0 "register_operand" "=r")
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(any_maxmin:I12MODE
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(match_operand:I12MODE 1 "reg_or_0_operand" "%rJ")
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(match_operand:I12MODE 2 "reg_or_8bit_operand" "rI")))]
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"TARGET_MAX"
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"minsb8 %r1,%2,%0"
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[(set_attr "type" "mvi")])
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(define_insn "uminqi3"
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[(set (match_operand:QI 0 "register_operand" "=r")
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(umin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
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(match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
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"TARGET_MAX"
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"minub8 %r1,%2,%0"
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[(set_attr "type" "mvi")])
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(define_insn "smaxqi3"
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[(set (match_operand:QI 0 "register_operand" "=r")
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(smax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
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(match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
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"TARGET_MAX"
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"maxsb8 %r1,%2,%0"
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[(set_attr "type" "mvi")])
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(define_insn "umaxqi3"
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[(set (match_operand:QI 0 "register_operand" "=r")
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(umax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
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(match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
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"TARGET_MAX"
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"maxub8 %r1,%2,%0"
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[(set_attr "type" "mvi")])
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(define_insn "sminhi3"
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[(set (match_operand:HI 0 "register_operand" "=r")
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(smin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
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(match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
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"TARGET_MAX"
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"minsw4 %r1,%2,%0"
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[(set_attr "type" "mvi")])
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(define_insn "uminhi3"
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[(set (match_operand:HI 0 "register_operand" "=r")
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(umin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
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(match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
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"TARGET_MAX"
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"minuw4 %r1,%2,%0"
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[(set_attr "type" "mvi")])
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(define_insn "smaxhi3"
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[(set (match_operand:HI 0 "register_operand" "=r")
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(smax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
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(match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
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"TARGET_MAX"
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"maxsw4 %r1,%2,%0"
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[(set_attr "type" "mvi")])
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(define_insn "umaxhi3"
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[(set (match_operand:HI 0 "register_operand" "=r")
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(umax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
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(match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
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"TARGET_MAX"
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"maxuw4 %r1,%2,%0"
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"<maxmin><vecmodesuffix> %r1,%2,%0"
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[(set_attr "type" "mvi")])
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(define_expand "smaxdi3"
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@ -4848,6 +4801,7 @@
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;; Vector operations
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(define_mode_iterator VEC [V8QI V4HI V2SI])
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(define_mode_iterator VEC12 [V8QI V4HI])
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(define_expand "mov<mode>"
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[(set (match_operand:VEC 0 "nonimmediate_operand" "")
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@ -4898,68 +4852,13 @@
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[(set_attr "type" "ilog,multi,ild,ist,fcpys,fld,fst,ftoi,itof")
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(set_attr "isa" "*,*,*,*,*,*,*,fix,fix")])
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(define_insn "uminv8qi3"
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[(set (match_operand:V8QI 0 "register_operand" "=r")
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(umin:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
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(match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
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(define_insn "<code><mode>3"
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[(set (match_operand:VEC12 0 "register_operand" "=r")
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(any_maxmin:VEC12
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(match_operand:VEC12 1 "reg_or_0_operand" "rW")
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(match_operand:VEC12 2 "reg_or_0_operand" "rW")))]
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"TARGET_MAX"
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"minub8 %r1,%r2,%0"
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[(set_attr "type" "mvi")])
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(define_insn "sminv8qi3"
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[(set (match_operand:V8QI 0 "register_operand" "=r")
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(smin:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
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(match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
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"TARGET_MAX"
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"minsb8 %r1,%r2,%0"
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[(set_attr "type" "mvi")])
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(define_insn "uminv4hi3"
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[(set (match_operand:V4HI 0 "register_operand" "=r")
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(umin:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW")
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(match_operand:V4HI 2 "reg_or_0_operand" "rW")))]
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"TARGET_MAX"
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"minuw4 %r1,%r2,%0"
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[(set_attr "type" "mvi")])
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(define_insn "sminv4hi3"
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[(set (match_operand:V4HI 0 "register_operand" "=r")
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(smin:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW")
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(match_operand:V4HI 2 "reg_or_0_operand" "rW")))]
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"TARGET_MAX"
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"minsw4 %r1,%r2,%0"
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[(set_attr "type" "mvi")])
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(define_insn "umaxv8qi3"
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[(set (match_operand:V8QI 0 "register_operand" "=r")
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(umax:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
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(match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
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"TARGET_MAX"
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"maxub8 %r1,%r2,%0"
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[(set_attr "type" "mvi")])
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(define_insn "smaxv8qi3"
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[(set (match_operand:V8QI 0 "register_operand" "=r")
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(smax:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
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(match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
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"TARGET_MAX"
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"maxsb8 %r1,%r2,%0"
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[(set_attr "type" "mvi")])
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(define_insn "umaxv4hi3"
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[(set (match_operand:V4HI 0 "register_operand" "=r")
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(umax:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW")
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(match_operand:V4HI 2 "reg_or_0_operand" "rW")))]
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"TARGET_MAX"
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"maxuw4 %r1,%r2,%0"
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[(set_attr "type" "mvi")])
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(define_insn "smaxv4hi3"
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[(set (match_operand:V4HI 0 "register_operand" "=r")
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(smax:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW")
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(match_operand:V4HI 2 "reg_or_0_operand" "rW")))]
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"TARGET_MAX"
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"maxsw4 %r1,%r2,%0"
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"<maxmin><modesuffix> %r1,%r2,%0"
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[(set_attr "type" "mvi")])
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(define_insn "one_cmpl<mode>2"
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