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alpha.md (vecmodesuffix): New mode attribute. 

* config/alpha/alpha.md (vecmodesuffix): New mode attribute.
	(modesuffix): Handle V8QI and V4HI modes.
	(any_maxmin): New code iterator.
	(maxmin): New code attribute.
	(<code><mode>3): Macroize insn from {smax,smin,umax,umin}{qi,hi}3
	using any_maxmin code iterator and I12MODE mode iterator.
	(<code><mode>3): Macroize insn from {smax,smin,umax,umin}{v8qi,v4hi}3
	using any_maxmin code iterator and VEC12 mode iterator.

From-SVN: r192396
This commit is contained in:
Uros Bizjak 2012-10-12 13:32:02 +02:00 committed by Uros Bizjak
parent 3b06f98418
commit 87218838b8
2 changed files with 34 additions and 124 deletions
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13
gcc/ChangeLog
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@ -1,3 +1,14 @@
2012-10-12 Uros Bizjak <ubizjak@gmail.com>
* config/alpha/alpha.md (vecmodesuffix): New mode attribute.
(modesuffix): Handle V8QI and V4HI modes.
(any_maxmin): New code iterator.
(maxmin): New code attribute.
(<code><mode>3): Macroize insn from {smax,smin,umax,umin}{qi,hi}3
using any_maxmin code iterator and I12MODE mode iterator.
(<code><mode>3): Macroize insn from {smax,smin,umax,umin}{v8qi,v4hi}3
using any_maxmin code iterator and VEC12 mode iterator.
2012-10-12 Marc Glisse <marc.glisse@inria.fr> 2012-10-12 Marc Glisse <marc.glisse@inria.fr>
* optabs.c (vector_compare_rtx): Change prototype. * optabs.c (vector_compare_rtx): Change prototype.
@ -62,7 +73,7 @@
*mov{qi,hi,si,di}cc_lbc using IMODE mode iterator. *mov{qi,hi,si,di}cc_lbc using IMODE mode iterator.
(*mov<mode>cc_lbs): Macroize insn from (*mov<mode>cc_lbs): Macroize insn from
*mov{qi,hi,si,di}cc_lbs using IMODE mode iterator. *mov{qi,hi,si,di}cc_lbs using IMODE mode iterator.
(mov<mode>cc): Macroize insn from mov{si,di}cc_lbs (mov<mode>cc): Macroize expander from mov{si,di}cc
using I48MODE mode iterator. using I48MODE mode iterator.
2012-10-11 Steven Bosscher <steven@gcc.gnu.org> 2012-10-11 Steven Bosscher <steven@gcc.gnu.org>

145
gcc/config/alpha/alpha.md
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@ -95,8 +95,16 @@
(define_mode_iterator I124MODE [QI HI SI]) (define_mode_iterator I124MODE [QI HI SI])
(define_mode_iterator I248MODE [HI SI DI]) (define_mode_iterator I248MODE [HI SI DI])
(define_mode_iterator I48MODE [SI DI]) (define_mode_iterator I48MODE [SI DI])
(define_mode_attr DWI [(SI "DI") (DI "TI")]) (define_mode_attr DWI [(SI "DI") (DI "TI")])
(define_mode_attr modesuffix [(QI "b") (HI "w") (SI "l") (DI "q")]) (define_mode_attr modesuffix [(QI "b") (HI "w") (SI "l") (DI "q")
(V8QI "b8") (V4HI "w4")])
(define_mode_attr vecmodesuffix [(QI "b8") (HI "w4")])
(define_code_iterator any_maxmin [smax smin umax umin])
(define_code_attr maxmin [(smax "maxs") (smin "mins")
(umax "maxu") (umin "minu")])
;; Where necessary, the suffixes _le and _be are used to distinguish between ;; Where necessary, the suffixes _le and _be are used to distinguish between
;; little-endian and big-endian patterns. ;; little-endian and big-endian patterns.
@ -2723,68 +2731,13 @@
(match_dup 0) (match_dup 1)))] (match_dup 0) (match_dup 1)))]
"") "")
(define_insn "sminqi3" (define_insn "<code><mode>3"
[(set (match_operand:QI 0 "register_operand" "=r") [(set (match_operand:I12MODE 0 "register_operand" "=r")
(smin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ") (any_maxmin:I12MODE
(match_operand:QI 2 "reg_or_8bit_operand" "rI")))] (match_operand:I12MODE 1 "reg_or_0_operand" "%rJ")
(match_operand:I12MODE 2 "reg_or_8bit_operand" "rI")))]
"TARGET_MAX" "TARGET_MAX"
"minsb8 %r1,%2,%0" "<maxmin><vecmodesuffix> %r1,%2,%0"
[(set_attr "type" "mvi")])
(define_insn "uminqi3"
[(set (match_operand:QI 0 "register_operand" "=r")
(umin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
(match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
"TARGET_MAX"
"minub8 %r1,%2,%0"
[(set_attr "type" "mvi")])
(define_insn "smaxqi3"
[(set (match_operand:QI 0 "register_operand" "=r")
(smax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
(match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
"TARGET_MAX"
"maxsb8 %r1,%2,%0"
[(set_attr "type" "mvi")])
(define_insn "umaxqi3"
[(set (match_operand:QI 0 "register_operand" "=r")
(umax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
(match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
"TARGET_MAX"
"maxub8 %r1,%2,%0"
[(set_attr "type" "mvi")])
(define_insn "sminhi3"
[(set (match_operand:HI 0 "register_operand" "=r")
(smin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
(match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
"TARGET_MAX"
"minsw4 %r1,%2,%0"
[(set_attr "type" "mvi")])
(define_insn "uminhi3"
[(set (match_operand:HI 0 "register_operand" "=r")
(umin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
(match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
"TARGET_MAX"
"minuw4 %r1,%2,%0"
[(set_attr "type" "mvi")])
(define_insn "smaxhi3"
[(set (match_operand:HI 0 "register_operand" "=r")
(smax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
(match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
"TARGET_MAX"
"maxsw4 %r1,%2,%0"
[(set_attr "type" "mvi")])
(define_insn "umaxhi3"
[(set (match_operand:HI 0 "register_operand" "=r")
(umax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
(match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
"TARGET_MAX"
"maxuw4 %r1,%2,%0"
[(set_attr "type" "mvi")]) [(set_attr "type" "mvi")])
(define_expand "smaxdi3" (define_expand "smaxdi3"
@ -4848,6 +4801,7 @@
;; Vector operations ;; Vector operations
(define_mode_iterator VEC [V8QI V4HI V2SI]) (define_mode_iterator VEC [V8QI V4HI V2SI])
(define_mode_iterator VEC12 [V8QI V4HI])
(define_expand "mov<mode>" (define_expand "mov<mode>"
[(set (match_operand:VEC 0 "nonimmediate_operand" "") [(set (match_operand:VEC 0 "nonimmediate_operand" "")
@ -4898,68 +4852,13 @@
[(set_attr "type" "ilog,multi,ild,ist,fcpys,fld,fst,ftoi,itof") [(set_attr "type" "ilog,multi,ild,ist,fcpys,fld,fst,ftoi,itof")
(set_attr "isa" "*,*,*,*,*,*,*,fix,fix")]) (set_attr "isa" "*,*,*,*,*,*,*,fix,fix")])
(define_insn "uminv8qi3" (define_insn "<code><mode>3"
[(set (match_operand:V8QI 0 "register_operand" "=r") [(set (match_operand:VEC12 0 "register_operand" "=r")
(umin:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW") (any_maxmin:VEC12
(match_operand:V8QI 2 "reg_or_0_operand" "rW")))] (match_operand:VEC12 1 "reg_or_0_operand" "rW")
(match_operand:VEC12 2 "reg_or_0_operand" "rW")))]
"TARGET_MAX" "TARGET_MAX"
"minub8 %r1,%r2,%0" "<maxmin><modesuffix> %r1,%r2,%0"
[(set_attr "type" "mvi")])
(define_insn "sminv8qi3"
[(set (match_operand:V8QI 0 "register_operand" "=r")
(smin:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
(match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
"TARGET_MAX"
"minsb8 %r1,%r2,%0"
[(set_attr "type" "mvi")])
(define_insn "uminv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=r")
(umin:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW")
(match_operand:V4HI 2 "reg_or_0_operand" "rW")))]
"TARGET_MAX"
"minuw4 %r1,%r2,%0"
[(set_attr "type" "mvi")])
(define_insn "sminv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=r")
(smin:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW")
(match_operand:V4HI 2 "reg_or_0_operand" "rW")))]
"TARGET_MAX"
"minsw4 %r1,%r2,%0"
[(set_attr "type" "mvi")])
(define_insn "umaxv8qi3"
[(set (match_operand:V8QI 0 "register_operand" "=r")
(umax:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
(match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
"TARGET_MAX"
"maxub8 %r1,%r2,%0"
[(set_attr "type" "mvi")])
(define_insn "smaxv8qi3"
[(set (match_operand:V8QI 0 "register_operand" "=r")
(smax:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
(match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
"TARGET_MAX"
"maxsb8 %r1,%r2,%0"
[(set_attr "type" "mvi")])
(define_insn "umaxv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=r")
(umax:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW")
(match_operand:V4HI 2 "reg_or_0_operand" "rW")))]
"TARGET_MAX"
"maxuw4 %r1,%r2,%0"
[(set_attr "type" "mvi")])
(define_insn "smaxv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=r")
(smax:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW")
(match_operand:V4HI 2 "reg_or_0_operand" "rW")))]
"TARGET_MAX"
"maxsw4 %r1,%r2,%0"
[(set_attr "type" "mvi")]) [(set_attr "type" "mvi")])
(define_insn "one_cmpl<mode>2" (define_insn "one_cmpl<mode>2"